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High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface
FEATURES
* * * * * * * * * * Four independent full-duplex asynchronous 16C950 high performance UART channels 128-byte deep FIFO per transmitter and receiver UARTs fully software compatible with industry standard 16C55x type UARTs Pin compatible with TL16C554 and ST16C654 Baud rates up to 15 Mbps in normal mode and 60Mbps in external 1x clock (isochronous) mode Readable FIFO levels Flexible clock prescaler from 1 to 31.875 Automated in-band flow control using programmable Xon/Xoff characters, in both directions Automated out-of-band flow control using CTS#/RTS# and/or DSR#/DTR# Arbitrary trigger levels for receiver and transmitter FIFO interrupts and automatic in-band and out-ofband flow control * * * * * * * * * * * * * * Readable in-band and out-of-band flow control status Programmable special character detection Infra-red (IrDA) receiver and transmitter option 5, 6, 7, 8 and 9-bits data framing Detection of bad data in the receiver FIFO Independent channel reset by software Transmitter and receiver can be disabled Transmitter idle interrupt RS-485 buffer enable signals Four byte device ID Sleep mode (low operating current) System clock up to 60 MHz at 5V, 50 MHz at 3.3V 5.0 volt or 3.3v operation* 68pin PLCC and 80pin TQFP package options.
*Only the 80pin TQFP package supports operation at 5v or 3.3v.
OX16C954 rev B
REV B ENHANCEMENTS
The OX16C954B is an enhanced, backward-compatible revision of the OX16C954 rev A. It uses the newer core as in the OX16C950 rev B. The chief enhancements are as follows - * All known errata fixed * Full TCR range from 4-16 * Enhanced controls for sleep-mode sensitivity, ability to read FCR and Good Data Status * 3.3V operation with 80 pin TQFP * Enhanced isochronous clocking options (optional inversions, DTR/DSR) Hereafter OX16C954 rev B is simply referred to as OX16C954.
Oxford Semiconductor Ltd. 25 Milton Park, Abingdon, Oxon, OX14 4SH, UK Tel: +44 (0)1235 824900 Fax: +44 (0)1235 821141
(c) Oxford Semiconductor 2001 OX16C954 rev B Data Sheet R1.0 - November 2001 Part Nos. OX16C954-PCC60-B / OX16C954_TQC60_B
DESCRIPTION
The OX16C954 is a single chip solution for 4 channel serial add-in cards. Each UART channel in the OX16C954 offers data rates up to 15Mbps and 128-byte deep transmitter and receiver FIFOs. Deep FIFOs reduce CPU overhead and allow utilisation of higher data rates. Each UART channel is software compatible with the widely used industry-standard 16C550 devices and compatibles, as well as the OX16C95x family of high performance UARTs. It is pin-compatible with the TL16C554, ST16C654 devices. In addition to increased performance and FIFO size, the UARTs also provide the full set of OX16C95x enhanced features. These include improved flow controls such as automated software flow control using Xon/Xoff and automated hardware flow control using CTS#/RTS# and DSR#/DTR# to prevent FIFO over-run. Flow control and interrupt thresholds are fully programmable and readable, enabling programmers to fine-tune the performance of their system. FIFO levels are readable to facilitate fast driver applications. The addition of software reset enables recovery from unforeseen error conditions allowing drivers to restart gracefully. The OX16C954 supports 9-bit data frames used in multi-drop industrial protocols. It also offers multiple external clock options for isochronous applications, e.g. ISDN, xDSL. The OX16C954 is ideally suited to PC applications, such as high-speed multi-port add-in cards that enable PC users to take advantage of the maximum performance of analogue modems or ISDN terminal adapters. It is also suitable for any equipment requiring high speed RS232/RS422/RS485 interfaces. Fabricated in 0.6m process, OX16C954 also has a low operating current and sleep mode for battery powered applications.
Oxford Semiconductor Ltd. 25 Milton Park, Abingdon, Oxon, OX14 4SH, UK Tel: +44 (0)1235 824900 Fax: +44 (0)1235 821141
(c) Oxford Semiconductor 2001 OX16C954 rev B Data Sheet R1.0 - November 2001 Part Nos. OX16C954-PCC60-B / OX16C954_TQC60_B
OXFORD SEMICONDUCTOR LTD.
OX16C954 rev B
CONTENTS
FEATURES .................................................................................................................................................................................................1 REV B ENHANCEMENTS.........................................................................................................................................................................1 DESCRIPTION............................................................................................................................................................................................ 2 CONTENTS.................................................................................................................................................................................................3 1 PERFORMANCE COMPARISON ......................................................................................................................................................5 2 BLOCK DIAGRAM............................................................................................................................................................................... 7 3 PIN INFORMATION .............................................................................................................................................................................8 4 PIN DESCRIPTIONS .........................................................................................................................................................................10 4.1 Further Pin Information ...........................................................................................................................................................15 5 MODE SELECTION ...........................................................................................................................................................................16 5.1 450 Mode ....................................................................................................................................................................................16 5.2 550 Mode ....................................................................................................................................................................................16 5.3 Extended 550 Mode ..................................................................................................................................................................16 5.4 750 Mode ....................................................................................................................................................................................16 5.5 650 Mode ....................................................................................................................................................................................16 5.6 950 Mode ....................................................................................................................................................................................17 6 REGISTER DESCRIPTION TABLES...............................................................................................................................................18 7 RESET CONFIGURATION................................................................................................................................................................22 7.1 Hardware Reset.........................................................................................................................................................................22 7.2 Software Reset ..........................................................................................................................................................................22 8 TRANSMITTER AND RECEIVER FIFOS ........................................................................................................................................23 8.1 FIFO Control Register `FCR' ...................................................................................................................................................23 9 LINE CONTROL & STATUS.............................................................................................................................................................24 9.1 False Start Bit Detection..........................................................................................................................................................24 9.2 Line Control Register `LCR' ....................................................................................................................................................24 9.3 Line Status Register `LSR' ......................................................................................................................................................25 10 INTERRUPTS & SLEEP MODE .......................................................................................................................................................26 10.1 Interrupt Enable Register `IER'...............................................................................................................................................26 10.2 Interrupt Status Register `ISR'................................................................................................................................................27 10.3 Interrupt Description ................................................................................................................................................................27 10.4 Sleep Mode.................................................................................................................................................................................28 11 MODEM INTERFACE........................................................................................................................................................................28 11.1 Modem Control Register `MCR'..............................................................................................................................................28 11.2 Modem Status Register `MSR'................................................................................................................................................29 12 OTHER STANDARD REGISTERS...................................................................................................................................................30 12.1 Divisor Latch Registers `DLL & DLM'....................................................................................................................................30 12.2 Scratch Pad Register `SPR'.....................................................................................................................................................30 13 AUTOMATIC FLOW CONTROL.......................................................................................................................................................31 13.1 Enhanced Features Register `EFR'........................................................................................................................................31 13.2 Special Character Detection ...................................................................................................................................................32 13.3 Automatic In-band Flow Control ............................................................................................................................................32 13.4 Automatic Out-of-band Flow Control ....................................................................................................................................32 14 BAUD RATE GENERATION.............................................................................................................................................................33 14.1 General Operation.....................................................................................................................................................................33 14.2 Clock Prescaler Register `CPR'..............................................................................................................................................34 14.3 Times Clock Register `TCR' ....................................................................................................................................................34 14.4 Input Clock Options..................................................................................................................................................................36 Data Sheet Revision 1.0 Page 3
OXFORD SEMICONDUCTOR LTD.
OX16C954 rev B
14.5 TTL Clock Mode ........................................................................................................................................................................36 14.6 External 1x Clock Mode...........................................................................................................................................................36 14.7 Crystal Oscillator Circuit .........................................................................................................................................................36 15 ADDITIONAL FEATURES ................................................................................................................................................................37 15.1 Additional Status Register `ASR'...........................................................................................................................................37 15.2 FIFO Fill levels `TFL & RFL'.....................................................................................................................................................37 15.3 Additional Control Register `ACR'.........................................................................................................................................37 15.4 Transmitter Trigger Level `TTL'..............................................................................................................................................39 15.5 Receiver Interrupt. Trigger Level `RTL'.................................................................................................................................39 15.6 Flow Control Levels `FCL' & `FCH' ........................................................................................................................................39 15.7 Device Identification Registers ..............................................................................................................................................39 15.8 Clock Select Register `CKS'....................................................................................................................................................40 15.9 Nine-bit Mode Register `NMR'.................................................................................................................................................40 15.10 Modem Disable Mask `MDM' ..............................................................................................................................................41 15.11 Readable FCR `RFC' ............................................................................................................................................................41 15.12 Good-data status register `GDS' .......................................................................................................................................41 15.13 DMA Status Register `DMS'................................................................................................................................................42 15.14 Port Index Register `PIX'.....................................................................................................................................................42 15.15 Clock Alteration Register `CKA' ........................................................................................................................................42 16 OPERATING CONDITIONS..............................................................................................................................................................43 17 DC ELECTRICAL CHARACTERISTICS .........................................................................................................................................44 17.1 5V Operation..............................................................................................................................................................................44 17.2 3.3V Operation...........................................................................................................................................................................45 18 AC ELECTRICAL CHARACTERISTICS .........................................................................................................................................46 18.1 5V Operation..............................................................................................................................................................................46 18.2 3.3V Operation...........................................................................................................................................................................47 19 TIMING WAVEFORMS......................................................................................................................................................................48 20 PACKAGE INFORMATION...............................................................................................................................................................50 21 ORDERING INFORMATION.............................................................................................................................................................52 NOTES ......................................................................................................................................................................................................53 CONTACT DETAILS................................................................................................................................................................................54
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OX16C954 rev B
1
PERFORMANCE COMPARISON
Feature Integrated Serial channels Good-Data status External 1x baud rate clock Max baud rate in normal mode Max baud rate in 1x clock mode FIFO depth Sleep mode Auto Xon/Xoff flow Auto CTS#/RTS# flow Auto DSR#/DTR# flow No. of Rx interrupt thresholds No. of Tx interrupt thresholds No. of flow control thresholds Transmitter empty interrupt Readable status of flow control Readable FIFO levels Clock prescaler options Rx/Tx disable Software reset Device ID 9-bit data frames RS485 buffer enable Infra-red (IrDA) OX16C954 4 Yes Yes 15 Mbps 60 Mbps 128 Yes Yes Yes Yes 128 128 128 Yes Yes Yes 248 Yes Yes Yes Yes Yes Yes 16C454 4 No No 115 kbps n/a 1 No No No No 1 1 n/a No n/a n/a n/a No No No No No No 16C554 4 No No 115 kbps n/a 16 No No No No 4 1 n/a No No No n/a No No No No No No 16C654 4 No No 1.5 Mbps n/a 64 Yes Yes Yes No 4 4 4 No No No 2 No No No No No Yes 16C750 1 No No 1 Mbps n/a 64 Yes No Yes No 4 1 n/a No No No n/a No No No No No No
Table 1 OX16C954 performance compared with 16C454, 16C554, 16C654 and 16C750 devices Improvements of the OX16C954 over previous generations of PC UARTs: Deeper FIFOs: The OX16C954 offers 128-byte deep FIFOs for the transmitter and receiver. Higher data rates: Transmission and reception baud rates up to 15Mbps. A flexible clock prescaler offers division ratios of 1 to 31 7/8 in steps of 1/8 using a divide-by-"M N/8" circuitry. The flexible prescaler allows users to select from a wide variety of input clock frequencies as well as access to higher baud rates whilst maintaining compatibility with existing software drivers (see section 14.2). External clock option: The receiver can accept an external clock on the DSR# input. The transmitter can accept a 1x clock on the RI# input and/or assert its own (Nx) clock on the DTR# output. In 1x mode, asynchronous data may be transmitted and received at speeds up to 60 Mbps (see section 14.6). Automatic flow control: The UART automatically handles either or both in-band (software) flow control (transmitting and receiving Xon/Xoff characters) and out-of-band (hardware) flow control using the RTS#/CTS# or DSR#/DTR# modem control lines. Special character detection: The receiver can be programmed to generate an interrupt upon reception of a particular character value. Power-down: The device can be placed in `sleep mode' to conserve power Readable FIFO levels: Driver efficiency can be improved by using readable FIFO levels. Selectable trigger levels: The receiver FIFO threshold can be arbitrarily programmed. The transmitter FIFO threshold and
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OXFORD SEMICONDUCTOR LTD.
OX16C954 rev B
thresholds for automatic flow control can be programmed to operate at a variety of trigger levels. TX/RX Disable: The transmitter and receiver can be independently disabled. Additional status: Software drivers are able to read the status of in-band and out-of-band automatic flow control, and distinguish between XOFF and special character received interrupts. Software reset: The software driver may reset the device to recover from unforeseen or unusual error conditions. Transmitter empty interrupt: The transmitter can generate an interrupt when the FIFO and shift register are both empty.
RS485 buffer enable: The function of the DTR# pin may be re-assigned to bufferenable signal for RS485 line driver in half-duplex mode (see ACR[4:3] in section 15.3). Device ID: Four bytes of device ID are available to identify the OX16C954 device to software drivers. Infrared `IrDA' interface: The UART contains an IrDA compliant modulator and demodulator. 9-bit data framing The UART may be configured for use in 9-bit character framing for multi-drop protocols, where a tag ID (9th bit) differentiates address and data characters. Dual Voltage Operation(TQFP) The 80pin TQFP package option can operate with supply voltages of either 5.0v or 3.3v, thereby reducing inventory controls. The VDETECT pin will need to be set according to the voltage environment.
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OX16C954 rev B
2
BLOCK DIAGRAM
A[2:0] D[7:0] CS0# / CS# CS1# / A[3] CS2# / A[4] CS3# I/M# IOR# Intel & Motorola Bus Interface
SERIAL CHANNEL n ( 1 of 4 shown )
Transmitter 128 Byte FIFO
SOUTn
Receiver
SINn
128 Byte FIFO
Internal Control Bus
IOW# / R/W# VDD GND FIFOSEL RESET / RESET# RXRDY# TXRDY# Control and DMA Interface
2 4
Power supply
Internal Data Bus
Control and Status Registers
RTSn# DTRn# OUT1n Modem Control Interface OUT2n CTSn# DSRn# DCDn#
XTLI XTLO CLKSEL Clock & Baud Rate Generator
RIn#
Interrupt Control Logic
INTn
INTEN#
VDETECT*
5v / 3.3v IO Buffer Control
NOTE : VDETECT pin is only available on the 80pin TQFP package option
Figure 1: OX16C954 Block Diagram
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OX16C954 rev B
3
PIN INFORMATION
68pin PLCC
DC D0 #
RI 0#
SI N0
GN D
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
DB 0
IN TS EL #
FIF OS EL #
SI N3
RI 3#
DC D3 #
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61 60 59 58 57 56 55 54 53
DSR0# CTS0# DTR0# VDD RTS0# INT0 / IRQ# CS0# / DS# SOUT0 IOW # / R/W # SOUT1 CS1# / A3 INT1 RTS1# GND DTR1# CTS1# DSR1#
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
DSR3# CTS3# DTR3# GND RTS3# INT3 CS3# SOUT3 IOR# SOUT2 CS2# / A4 INT2 RTS2# VDD DTR2# CTS2# DSR2#
OX16C954-PCC60-B
52 51 50 49 48 47 46 45 44
DC D1 #
RI 1#
SI N1
CL KS EL
I/M #
A2
A1
A0
XT LI
XT LO
RE SE T/ RE SE T#
37
38
39
40
41
42
43
RX RD Y#
TX RD Y#
GN D
SI N2
RI 2#
DC D2 #
OX16C954-PCC60-B (Rev B) is pin compatible with the previous part OX16C954-PCC60-A (Rev A).
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80pin TQFP
OX16C954 rev B
RXRDY3#
CS2# / A4
SOUT3
SOUT2
80 TXRDY3# DCD3# RI3# SIN3 FIFOSEL# INTSEL# DB0 DB1 DB2 NC DB3 DB4 DB5 DB6 DB7 GND SIN0 RI0# DCD0# RXRDY0# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 OX16C954_TQC60_B 51 50 49 48 47 46 45 44 43 42 RXRDY2# DCD2# RI2# SIN2 GND TXRDY# RXRDY# RESET/RESET# VDETECT XTLO XTLI I/M# A0 A1 A2 CLKSEL SIN1 RI1# DCD1# TXRDY1#
41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NC
INT1
DTR0#
GND
VDD
DSR0#
DTR1#
SOUT0
SOUT1
DSR1#
CTS0#
RTS0#
RTS1#
CTS1#
DSR2#
RTS2#
CS3#
IOR#
INT3
INT2
VDD
NC
INT0 / IRQ#
CS0# / DS#
Data Sheet Revision 1.0
IOW# / R/R#
RXRDY1#
TXRDY0#
CS1# / A3
TXRDY2#
Z_RTS3
DSR3#
DTR3#
DTR2#
CTS3#
CTS2#
GND
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OX16C954 rev B
4
PIN DESCRIPTIONS
Please refer to Section 3 for actual Signal Name to Pin Number assignments, for the selected package. TQFP Clock 50 51 45 PLCC 35 36 30 Dir1 I O I Name XTLI XTLO CLKSEL Description Crystal oscillator input or external clock pin, for the UART channels. Crystal oscillator frequency maximum 60MHz Crystal oscillator output. Not used when an alternative TTL level clock is applied to XTLI and can be left unconnected This pin is provided to select an internal clock prescaler on power up. In 16C554 devices this pin is a VDD. When CLKSEL pin is high the internal prescaler is bypassed (a 1.8432MHz clock is assumed). Connect this pin to GND to enable the internal clock prescaler. The complement of this pin is loaded in bit 7 of the MCR register after a hardware reset.
This pin can also be used as an alternative external clock pin under software control (replacing XTLI and thus reducing noise/power due to XTLO) for embedded applications. Processor Interface Pins in Intel Mode (I/M# = `1') 53 37 I RESET Active-high Hardware Reset. The configuration of OX16C954 after a hardware reset is described in section 7.1. This pin exhibits a small hysteresis to provide noise immunity. This pin must be tied inactive when not in use. Active-low Chip-Selects for each Uart channel, in Intel bus mode. 73 54 I CS[3]# CS3# - Chip select for Uart 3 68 50 I CS[2]# CS2# - Chip select for Uart 2 33 20 I CS[1]# CS1# - Chip select for Uart 1 28 16 I CS[0]# CS0# - Chip select for Uart 0 46 to 48 15 to 11 9 to 7 31 70 Processor 53 32 to 34 I A[2:0] Address lines to select the Uart (channel) registers.
28
5 to 1 I/O DB[7:0] Eight-bit 3-state data bus. 68 to 66 18 I IOW# Active-low write strobe in Intel bus mode. 52 I IOR# Active-low read strobe in Intel bus mode. Interface Pins in Motorola Mode (I/M# = `0') 37 I RESET# Active-low Hardware Reset. The configuration of OX16C954 after a hardware reset is described in section 7.1. This pin exhibits a small hysteresis to provide noise immunity. This pin must be tied inactive when not in use. 16 I DS# Active-low Data-Strobe. (In Motorola bus mode, individual registers are accessed using DS#, R/W# and A[4:0]) 52 54 50 20 I I I I UNUSED A4 A3 In Motorola bus mode these pins are unused and must be connected to VDD or GND. The A[4:3] combination selects individual channels as follows: 00 = UART 0 selected 01 = UART 1 selected 10 = UART 2 selected 11 = UART 3 selected Address lines to select the UART (channel) registers.
70 73 68 33
46 to 48
32 to 34
I
A[2:0]
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TQFP Processor 15 to 11 9 to 7 31
OX16C954 rev B
PLCC Dir1 Name Description Interface Pins in Motorola Mode (I/M# = `0') Contd. 5 to 1 I/O DB[7:0] Eight-bit 3-state data bus. 68 to 66 18 I R/W# Read-not-write signal. This signal should be high during read cycles and low during write cycles. O O O O O O O O O O O O SOUT[3] SOUT[2] SOUT[1] SOUT[0] IrDA_Out[3] IrDA_Out[2] IrDA_Out[1] IrDA_Out[0] RTS[3]# RTS[2]# RTS[1]# RTS[0]# Serial data output, Uart 3 Serial data output, Uart 2 Serial data output, Uart 1 Serial data output, Uart 0 UART IrDA data outputs, each Uart, respectively. Serial data output pins are redefined as IrDA data outputs when MCR[6] of the corresponding UART channel is set in enhanced mode Active-low Request-To-Send output, for each uart respectively. Whenever the automated RTS# flow control is enabled for the corresponding channel, the RTS# pin is de-asserted and re-asserted if the receiver FIFO reaches or falls below a pair of programmed flow control thresholds, respectively. The state is controlled by bit 1 of the MCR. RTS may also be used as a general-purpose output. Active-low modem "data-terminal-ready output", for each uart respectively. If automated DTR# flow control is enabled for the corresponding UART channel, the DTR# pin is asserted and deasserted if the receiver FIFO reaches or falls below the channel's programmed thresholds, respectively. The state is set by bit 0 of the MCR. DTR may also be used as a general purpose output. In RS485 half-duplex mode, the DTR# pin of each UART channel may be programmed to reflect the state of the channel's transmitter empty bit (or its inverse) to automatically control the direction of the RS485 transceiver buffer (see register ACR[4:3]) Transmitter 1x (or baud rate generator output) clock. For isochronous applications, the 1x (or Nx) transmitter clock may be asserted on the uart's DTR# pin (see CKS[5:4]). Serial data input, UART 3. Serial data input, UART 2. Serial data input, UART 1. Serial data input, UART 0. UART IrDA data inputs, for each uart respectively. Serial data input pins redefined as IrDA data inputs when MCR[6] of the corresponding UART channel is set in enhanced mode Active-low modem "clear-to-send" input, for each uart respectively. If automated CTS# flow control is enabled for the corresponding UART channel, upon deassertion of the CTS# pin, the channel's transmitter will complete the current character and enter the idle mode until the CTS# pin is reasserted. Note: flow control characters are transmitted regardless of the state of the CTS# pin. The state of this pin is reflected in bit 4 of the MSR. It can also be used as a general-purpose input. Page 11
Serial Port Pins 53 72 51 69 19 32 17 29 72 69 32 29 75 66 35 26 53 51 19 17 56 48 22 14
77 64 37 24 77 64 37 24 77 64 37 24 4 57 44 17 4 57 44 17 78 63 38 23
58 46 24 12 58 46 24 12 58 46 24 12 63 41 29 7 63 41 29 7 59 45 25 11
O O O O O O O O O O O O I I I I I I I I I I I I
DTR[3]# DTR[2]# DTR[1]# DTR[0]# 485_En[3] 485_En[2] 485_En[1] 485_En[0] TxClkOut[3] TxClkOut[2] TxClkOut[1] TxClkOut[0] SIN[3] SIN[2] SIN[1] SIN[0] IrDA_In[0:3] IrDA_In[0:3] IrDA_In[0:3] IrDA_In[0:3] CTS[3]# CTS[2]# CTS[1]# CTS[0]#
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TQFP PLCC Dir1 Serial Port Pins Contd. I 60 79 I 44 62 I 26 39 I 10 22 Name DSR[3]# DSR[2]# DSR[1]# DSR[0]# Description
OX16C954 rev B
Active-low modem "data-set-ready" input, for each uart respectively. If automated DSR# flow control is enabled for the corresponding UART channel, upon deassertion of the channel's DSR# pin, the transmitter will complete the current character and enter the idle mode until the DSR# pin is reasserted. Note: flow control characters are transmitted regardless of the state of the DSR# pin. The state of this pin is reflected in bit 5 of the MSR. It can also be used as a general-purpose input. External receiver clock for isochronous applications for each uart respectively. Selected when CKS[1:0] = `01'.
79 62 39 22 2 59 42 19 3 58 43 18 3 58 43 18
60 44 26 10 61 43 27 9 62 42 28 8 62 42 28 8
I I I I I I I I I I I I I I I I
RxClkIn[3] RxClkIn[2] RxClkIn[1] RxClkIn[0] DCD[3]# DCD[2]# DCD[1]# DCD[0]# RI[3]# RI[2]# RI[1]# RI[0]# Ext_CK[3] Ext_CK[2] Ext_CK[1] Ext_CK[0] TXRDY3# TXRDY2# TXRDY1# TXRDY0#
Active-low modem Data-Carrier-Detect input, for each uart respectively. The state of this pin is reflected in bit 7 of the MSR. It can also be used as a general-purpose input. Active-low modem Ring-Indicator input, for each uart respectively. The state of this pin is reflected in bit 6 of the MSR. It can also be used as a general-purpose input. RI can be configured as tx and rx for a 1x clock in isochronous operation. External transmitter clock for each uart respectively. This clock can be used by the transmitter (and by the receiver indirectly) when CKS[6] = `1'.
Interrupt & DMA Pins 1 No pin O 61 No pin O 41 No pin O 21 No pin O
Signal for the DMA transfer of transmitter data, for Uart 3. Signal for the DMA transfer of transmitter data, for Uart 2. Signal for the DMA transfer of transmitter data, for Uart 1. Signal for the DMA transfer of transmitter data, for Uart 0. There are two modes of DMA signalling described in section 8.1
55
39
O
TXRDY#
Signal for the DMA transfer of transmitter data. This pin is the wire "OR-ed" function of the TXRDY# signals of all channels. Signal for the DMA transfer of receiver data, for Uart 3. Signal for the DMA transfer of receiver data, for Uart 2. Signal for the DMA transfer of receiver data, for Uart 1. Signal for the DMA transfer of receiver data, for Uart 0. There are two modes of DMA signalling described in section 8.1
80 60 40 20
No pin No pin No pin No pin
O O O O
RXRDY3# RXRDY2# RXRDY1# RXRDY0#
54
38
O
RXRDY#
Signal for DMA transfer of received data. This pin is the wire "OR-ed" function of the RXRDY# signals of all channels.
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TQFP PLCC Dir1 Name Interrupt & DMA Pins Contd. INT[3] O 55 74 INT[2] O 49 67 INT[1] O 21 34 Description Interrupt pin for Uart channel 3 (Intel Bus mode) Interrupt pin for Uart channel 2 (Intel Bus mode) Interrupt pin for Uart channel 1 (Intel Bus mode)
OX16C954 rev B
27
15
O
INT0
Each of these serial channels have a 3-state interrupt output (enabled by MCR[3] and INTSEL# pin) which goes active (high) when an interrupt condition occurs. The interrupt is disabled after a hardware reset. Interrupt pin for Uart channel 0, in Intel bus mode. This serial channel has a 3-state interrupt output (enabled by MCR[3] and INTSEL# pin) which goes active (high) when an interrupt condition occurs. The interrupt is disabled after a hardware reset. Device interrupt pin (for all uart channels) in Motorola bus mode. This pin goes active (low) when the interrupt signal from any of the 4 channels is asserted. Otherwise it is in the high-impedance state. Active-low Interrupt enable. When this pin is left open or connected to GND, the three-state interrupts that are available on INT[3:0] are enabled according to the setting of MCR[3]. If this pin is high interrupts are enabled regardless of the state of MCR[3]. This pin is ignored in Motorola bus mode. Intel or Motorola bus interface select. When this pin is tied high or left open, the Intel bus interface is selected. When this pin is tied low, the Motorola bus interface is selected where RESET, IOW#, CS0#, CS1# are CS2# are re-assigned and CS3#, IOR# and INTSEL# are unused. In Motorola mode, all the interrupt lines of the internal uart channels are wired "OR-ed" onto the IRQ# pin. In 16C554 this pin is unconnected. FIFO SIZE select. For backward compatibility with 16C554, 16C654 and 16C754 devices the FIFO depth is 16 when FIFOSEL# is high and 128 when FIFOSEL# is low. The unlatched state of this pin is readable by software. The FIFO size may be set to 128 by writing a 1 in FCR[5] when LCR[7] is set or by putting the device into Enhanced mode, thus overriding the state of the FIFOSEL# pin. Pin 64 is a VDD in 16C554 and 16C654 devices (PLCC). 3.3v or 5.0v I/O buffer selection. This pin must be tied according to the voltage supply used to power the TQFP package option. For 5v supply voltage : Vdetect must be tied low. For 3.3v supply voltage : Vdetect must be tied high. NOTE : The PLCC package option does not bond-out this pin, which is internally pulled down to gnd. So the PLCC is suitable for 5v operation only.
27
15
OD
IRQ#
Miscellaneous Pins 6 65 ID
INTSEL#
49
31
IU
I/M#
5
64
I
FIFOSEL#
52
No pin
ID
VDETECT
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OXFORD SEMICONDUCTOR LTD.
TQFP PLCC Dir1 Name Power, Ground, No Connects 16, 36, 6, 23, GND 56, 76 40, 57 25, 65 13, 47 VDD Description Ground pin. All GND pins must be tied to ground.
OX16C954 rev B
10, 30, 71
-
NC
Power pin. PLCC : All VDD pins must be tied to 5 Volts. TQFP : All VDD pins must be tied to 5v or 3.3v. (Note that the VDETECT pin must be set according to the selected voltage environment). No Connects These pins are not connected to any pads within the device, and can be left open.
Table 2: Pin Descriptions
Direction key: I, Input IU Input with pull-up ID Input with pull-down O Output I/O Bi-directional OD Open drain Note: All unused signal input pins should be tied to VDD or GND as applicable and must not be left floating. For high speed operation (XTAL > 10MHz), card designers are recommended to follow the guidelines for high-speed digital design such as maintaining PCB tracks as short as possible, using a multi-layer PCB with separate power and ground planes, and using good-quality de-coupling capacitors. Attention should be given to high frequency decoupling of power and ground pins due to the high frequency internal switching that occurs under normal operation
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OX16C954 rev B
4.1
Pin
Further Pin Information
Description Action when used Action when not used
I/M# CS0#-CS3#
Intel TM Mode Bus Interface Pins Intel / Motorola Mode Tie high for IntelTM style bus mode Chip selects Connect direct to active low channel select signals for UART channels 0-3 respectively MotorolaTM Mode Bus Interface Pins Intel / Motorola Mode Tie low for Motorola TM style bus mode Data Strobe Connect direct to data strobe generator logic Additional address Connect direct to channel selection logic lines A[4:3] = 00 = ch. 1, 01 = ch. 2 etc. Global interrupt Interrupt for all channels. Connect to an available processor interrupt line Unused n/a Unused n/a Control Pins Tie high to keep the interrupt pins permanently enabled. DMA Pins Connect direct to DMA control circuitry Connect direct to DMA control circuitry Common Channel Pins Connect to a suitable line driver Connect to a suitable line receiver Connect to a suitable line driver Connect to a suitable line receiver Connect to a suitable line driver Connect to a suitable line receiver Connect to a suitable line receiver Connect to a suitable line receiver Connect to an available processor interrupt line
Leave unconnected (Internal pull-up) n/a
I/M# DS# (CS0#) A3-4 (CS1-2#) IRQ# (INT0) CS3# INT1-3
n/a Must be tied low for Motorola mode n/a n/a Leave unconnected (Interrupts can not be used) Tie high Leave unconnected
INTSEL
Interrupt Control Mode (used in Intel mode only) DMA Control signal output DMA Control signal output
Tie low or leave unconnected to allow software enable/disable of the interrupt pin. Leave unconnected Leave unconnected
RXRDY# TXRDY#
SOUT SIN RTS# CTS# DTR# DSR# DCD# RI# INT
Serial data output Serial data input Request-To-Send Modem signal output Clear-To-Send Modem signal input Data-Terminal-Ready Modem signal output Data-Set-Ready Modem signal input Data-Carrier-Detect Modem signal input Ring-Indicator Modem signal input Interrupt Output
Leave unconnected (Serial data can not be transmitted) Leave unconnected (Serial data can not be received) Leave unconnected Tie high Leave unconnected Tie high Tie high Tie high Leave unconnected (Interrupts can not be used)
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OX16C954 rev B
5
MODE SELECTION
The OX16C954 device is a four-channel device backward compatible with the 16C454, 16C554, 16C654 and 16C750 UARTs. Each of the four channels are identical and independent in terms of functionality, with the exception of some shared pins (for example, CLKSEL, FIFOSEL#, CLK and RESET). The remainder of this document therefore discusses the operation of a single channel only. The operation of each Uart Channel depends on a number of mode settings, which are referred to throughout this section. The modes, conditions and corresponding FIFO depth are tabulated below: UART Mode 450 550 Extended 550 650 750 9501 FIFO size 1 16 128 128 128 128 FCR[0] 0 1 1 1 1 1 Enhanced mode (EFR[4]=1) X 0 0 1 0 1 FCR[5] (guarded with LCR[7] = 1) X 0 X X 1 X FIFOSEL# Pin X 1 0 X 1 X
Note 1: 950 mode configuration is identical to 650 configuration
Table 3: UART Mode Configuration software should first set LCR[7] to temporarily remove the guard. Once FCR[5] is set, the software should clear LCR[7] for normal operation. The 16C750 additional features are available as long as the UART is not put into Enhanced mode; i.e. ensure EFR[4] = `0'. These features are: * * * Deeper FIFOs Automatic RTS/CTS out-of-band flow control Sleep mode
5.1
450 Mode
After a hardware reset, bit 0 of the FIFO Control Register (`FCR') is cleared, hence the UART is compatible with the 16C450. The transmitter and receiver FIFOs (referred to as the `Transmit Holding Register' and `Receiver Holding Register' respectively) have a depth of one. This is referred to as `Byte mode'. When FCR[0] is cleared, all other mode selection parameters are ignored.
5.2
550 Mode 5.5 650 Mode
The OX16C954 UART is compatible with the 16C650 when EFR[4] is set, i.e. the device is in Enhanced mode. As 650 software drivers usually put the device in Enhanced mode, running 650 drivers on the one of the UART channels will result in 650 compatibility with 128 deep FIFOs, as long as FCR[0] is set. Note that the 650 emulation mode of the OX16C954 provides 128-deep FIFOs whereas the standard 16C650 has only 32 byte FIFOs. 650 mode has the same enhancements as the 16C750 over the 16C550, but these are enabled using different registers. There are also additional enhancements over those of the 16C750 in this mode. These are 1. 2. Automatic in-band flow control Special character detection Page 16
Connect FIFOSEL# to VDD. After a hardware reset, writing a 1 to FCR[0] will increase the FIFO size to 16, providing compatibility with 16C550 devices. Since this pin is VDD in 16C554 devices, replacing a 16C554 with OX16C954 would result in a 550 compatible device with 16 byte deep FIFOs.
5.3
Extended 550 Mode
Connect FIFOSEL# to GND. Writing a 1 to FCR[0] will now increase the FIFO size to 128, thus providing a 550 device with 128 deep FIFOs.
5.4
750 Mode
Writing a 1 to FCR[0] will increase the FIFO size to 16. In a similar fashion to 16C750, the FIFO size can be further increased to 128 by writing a 1 to FCR[5]. Note that access to FCR[5] is protected by LCR[7]. i.e., to set FCR[5], Data Sheet Revision 1.0
OXFORD SEMICONDUCTOR LTD.
3. 4. 5. Infra-red "IrDA-format" transmit and receive mode Transmit trigger levels Optional clock prescaler
OX16C954 rev B
section 15). The Additional Status Register (`ASR') offers flow control status for the local and remote transmitters. FIFO levels are readable using RFL and TFL registers. The UART has a flexible prescaler capable of dividing the system clock by any value between 1 and 31.875 in steps of 0.125. It divides the system clock by an arbitrary value in "M+N/8" format, where M and N are 5- and 3-bit binary numbers programmed in CPR[7:3] and CPR[2:0] respectively. This arrangement offers a great deal of flexibility when choosing an input clock frequency to synthesise arbitrary baud rates. The default division value is 4 to provide backward compatibility with 16C650 devices. The user may apply an external 1x (or Nx) clock for the transmitter and receiver to the RI# and DSR# pin respectively. The transmitter clock may instead be asserted on the DTR# pin. The external clock options are selected through the CKS register (offset 0x02 of ICR). It is also possible to define the over-sampling rate used by the transmitter and receiver clocks. The 16C450/16C550 and compatible devices employ 16 times over-sampling, where there are 16 clock cycles per bit. However the 950 UART can employ any over-sampling rate from 4 to 16 by programming the TCR register. This allows the data rates to be increased to 460.8 Kbps using a 1.8432MHz clock, or 15 Mbps using a 60 MHz clock. The default value after a reset for this register is 0x00, which corresponds to a 16 cycle sampling clock. Writing 0x01, 0x02 or 0x03 will also result in a 16 cycle sampling clock. To program the value to any value from 4 to 15 it is necessary to write this value into the TCR i.e. to set the device to a 13 cycle sampling clock it would be necessary to write 0x0D to TCR. For further information see section 14.3. The UART also offers 9-bit data frames for multi-drop industrial applications.
5.6
950 Mode
The additional features offered in 950 mode generally only apply when the UART is in Enhanced mode (EFR[4]='1'). Provided FCR[0] is set, in Enhanced mode the FIFO size is 128 regardless of the state of FIFOSEL#. Note that 950 mode configuration is identical to that of 650 mode, however additional 950 specific features are enabled using the Additional Control Register `ACR' (see section 15.3). In addition to larger FIFOs and higher baud rates, the enhancements of the 950 mode over 650 emulation mode are: * * * * * * * * * * * * * Selectable arbitrary trigger levels for the receiver and transmitter FIFO interrupts Improved automatic flow control using selectable arbitrary thresholds DSR#/DTR# automatic flow control Transmitter and receiver can be optionally disabled Software reset of device Readable FIFO fill levels Optional generation of an RS-485 buffer enable signal Four-byte device identification (0x16C95404) Readable status for automatic in-band and out-ofband flow control External 1x clock modes (see section14.4) Flexible "M+N/8" clock prescaler (see section 14.2) Programmable sample clock to allow data rates up to 15 Mbps (see section 14.3). 9-bit data mode
The 950 trigger levels are enabled when ACR[5] is set (bits 4 to 7 of FCR are ignored). Then arbitrary trigger levels can be defined in RTL, TTL, FCL and FCH registers (see
Data Sheet Revision 1.0
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OX16C954 rev B
6
REGISTER DESCRIPTION TABLES
The UART is accessed through an 8-byte block of I/O space (or through memory space). Since there are more than 8 registers, the mapping is also dependent on the state of the Line Control Register `LCR' and Additional Control Register `ACR': 1. 2. 3. 4. LCR[7]=1 enables the divider latch registers DLL and DLM. LCR specifies the data format used for both transmitter and receiver. Writing 0xBF (an unused format) to LCR enables access to the 650 compatible register set. Writing this value will set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the data format of the transmitter and receiver data is not affected. Write the desired LCR value to exit from this selection. ACR[7]=1 enables access to the 950 specific registers. ACR[6]=1 enables access to the Indexed Control Register set (ICR) registers as described on page 20.
Register Name THR 1 RHR 1 IER 650/950 Mode
1,2
Address 000 000
R/W W R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data to be transmitted Data received CTS interrupt mask Special Char. Sleep Detect mode Alternate Unused sleep mode RHR Trigger THR Trigger Level Level RHR Trigger FIFO Unused Level Size Unused FIFOs enabled Divisor latch access Tx break Interrupt priority (Enhanced mode) Force parity CTS & RTS Flow Control XON-Any THR Empty Odd / even parity Enable Internal Loop Back Rx Break Parity enable RTS interrupt mask Modem interrupt mask DMA Mode / Tx Trigger Enable Rx Stat interrupt mask THRE interrupt mask RxRDY interrupt mask
001
R/W
550/750 Mode FCR 3 650 mode 750 mode 950 mode ISR 3 LCR 4 MCR 3,4 550/750 Mode 650/950 Mode LSR 3,5 Normal 9-bit data mode MSR 3 101 R 010 011 R R/W 010 W
Flush THR
Flush RHR
Enable FIFO
Interrupt priority (All modes) Number of stop bits OUT1 (not used)
Interrupt pending Data length
Unused 100 R/W Baud prescale Data Error IrDA mode Tx Empty
OUT2 (interrupt enable) Framing Error
RTS
DTR
110
R
DCD
RI
SPR 3 Normal 111 R/W 9-bit data 9th Tx Unused mode data bit Additional Standard Registers - These registers require divisor latch access bit (LCR[7]) to be set to 1. DLL DLM 000 001 R/W R/W Divisor latch bits [7:0] (Least significant byte) Divisor latch bits [15:8] (Most significant byte)
Parity Error 9th Rx data bit Delta Trailing DSR CTS DCD RI edge Temporary data storage register and Indexed control register offset value bits
Overrun Error
RxRDY
Delta DSR
Delta CTS
Table 4: Standard 550 Compatible Registers
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OXFORD SEMICONDUCTOR LTD.
Register Name EFR XON1 9-bit mode XON2 9-bit mode XOFF1 9-bit mode XOFF2 9-bit mode Address R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
OX16C954 rev B
Bit 1 Bit 0
010 100 101 110 111
R/W R/W R/W R/W R/W
To access these registers LCR must be set to 0xBF CTS Enhance In-band flow control mode RTS Special flow mode Flow char control control detect XON Character 1 Special character 1 XON Character 2 Special Character 2 XOFF Character 1 Special character 3 XOFF Character 2 Special character 4
Table 5: 650 Compatible Registers
Register Name ASR 1,6,7 RFL 6 TFL 3,6 ICR 3,8,9
Address 001 011 100 101
R/W R/W 7 R R R/W
Bit 7 Tx Idle
Bit 6 FIFO size
Bit 5 FIFOSEL
Bit 4
Bit 3
Bit 2
Bit 1 Remote Tx Disabled
Bit 0 Tx Disabled
DTR RTS Special Char Detect Number of characters in the receiver FIFO
Number of characters in the transmitter FIFO Data read/written depends on the value written to the SPR prior to the access of this register (see Table 7)
Table 6: 950 Specific Registers Register access notes:
Note 1: Requires LCR[7] = 0 Note 2: Requires ACR[7] = 0 Note 3: Requires that last value written to LCR was not 0xBF Note 4: To read this register ACR[7] must be = 0 Note 5: To read this register ACR[6] must be = 0 Note 6: Requires ACR[7] = 1 Note 7: Only bits 0 and 1 of this register can be written Note 8: To read this register ACR[6] must be = 1 Note 9: This register acts as a window through which to read and write registers in the Indexed Control Register set
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OXFORD SEMICONDUCTOR LTD.
Register Name ACR SPR Offset 10 0x00 R/W R/W Bit 7 Additional Status Enable Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
OX16C954 rev B
Bit 1 Bit 0
Indexed Control Register Set ICR 950 DTR definition and Read Trigger control Enable Level Enable
CPR TCR CKS TTL RTL FCL FCH ID1 ID2 ID3 REV CSR NMR MDM RFC GDS DMS PIDX CKA
0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0X0F 0X10 0x11 0x12 0x13
R/W R/W R/W R/W R/W R/W R/W R R R R W R/W R/W R R R/W R R/W Tx 1x Mode Unused Unused Unused Unused
Auto Tx Rx DSR Disable Disable Flow Control Enable 5 Bit "integer" part of 3 Bit "fractional" part of clock prescaler clock prescaler Unused 4 Bit N-times clock selection bits [3:0] Tx CLK BDOUT DTR 1x Rx 1x Unused Receiver Select on DTR Tx CLK Mode Clock Sel[1:0] Transmitter Interrupt Trigger Level (0-127) Receiver Interrupt Trigger Level (1-127) Automatic Flow Control Lower Trigger Level (0-127) Automatic Flow Control Higher Trigger level (1-127) Hardwired ID byte 1 (0x16) Hardwired ID byte 1 (0xC9) Hardwired ID byte 1 (0x54) Hardwired revision byte (0x04)
Writing 0x00 to this register will reset the UART (Except the CKS and CKA registers) Unused 9th Bit 9th Bit 9th Bit 9th Bit SChar 4 SChar 3 SChar 2 SChar 1 Trailing DCD RI edge Reserved Wakeup disable disable FCR[7] FCR[6] FCR[5] FCR[4] FCR[3] FCR[2] Unused Force TxRdy inactive
9th-bit Int. En. DSR Wakeup disable FCR[1]
TxRdy Force Unused status RxRdy inactive (R) Hardwired Port Index ( 0x00, 0x01, 0x02, 0x03 respectively ) Use Invert Invert Unused CLKSEL DTR internal pin for signal tx clock sys-clk
9 Bit Enable CTS Wakeup disable FCR[0] Good Data Status RxRdy status (R) Invert internal rx clock
Table 7: Indexed Control Register Set
Note 10: The SPR offset column indicates the value that must be written into SPR prior to reading / writing any of the Indexed Control Registers via ICR. Offset values not listed in the table are reserved for future use and must not be used.
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OXFORD SEMICONDUCTOR LTD.
To read or write to any of the Indexed Controlled Registers use the following procedure: Writing to ICR registers: Ensure that the last value written to LCR was not 0xBF (reserved for 650 compatible register access value). Write the desired offset to SPR (address 111b). Write the desired value to ICR (address 101b). Reading from ICR registers: Ensure that the last value written to LCR was not 0xBF (see above). Write 0x00 offset to SPR to select ACR. Set bit 6 of ACR (ICR read enable) by writing x1xxxxxxb to address 101b. Ensure that other bits in ACR are not changed. (Software drivers should keep a copy of the contents of the ACR elsewhere since reading ICR involves overwriting ACR!) Write the desired offset to SPR (address 111b). Read the desired value from ICR (address 101b). Write 0x00 offset to SPR to select ACR. Clear bit 6 of ACR bye writing x0xxxxxxb to ICR, thus enabling access to standard registers again.
OX16C954 rev B
Data Sheet Revision 1.0
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OX16C954 rev B
7
7.1
RESET CONFIGURATION
Hardware Reset 7.2 Software Reset
After a hardware reset, all writable registers are reset to 0x00, with the following exceptions: 1. DLL which is reset to 0x01. 2. MCR[7] is reset to the complement of the CLKSEL input pin value (see section 11.1 ). 3. CPR is reset to 0x20. The state of read-only registers following a hardware reset is as follows: RHR[7:0]: RFL[6:0]: TFL[6:0]: LSR[7:0]: MSR[3:0]: MSR[7:4]: ISR[7:0]: ASR[7:0]: RFC[7:0]: GDS[7:0]: DMS[7:0]: CKA[7:0]: Indeterminate 00000002 00000002 0x60 signifying that both the transmitter and the transmitter FIFO are empty 00002 Dependent on modem input lines DCD, RI, DSR and CTS respectively 0x01, i.e. no interrupts are pending 1xx000002 000000002 000000012 000000102 000000002
An additional feature available in the OX16C954 device is independent software resetting of any of the four serial channels. The software reset is available using the given channels CSR register. The Software reset command has the same effect as a hardware reset except it only resets the channel whose CSR register is written, the state of all other channels remains unchanged. Also it does not reset the clock source selections (i.e. CKS register and CKA register). To reset a channel, write 0x00 to the Channel Software Reset register `CSR'.
The reset state of output signals are tabulated below: Signal SOUTn RTSn# DTRn# INTn / IRQ# RXRDY# TXRDY# Reset state Inactive High Inactive High Inactive High Inactive low when INTSEL# pin is held high otherwise high-impedance Inactive High Active low (THR is able to receive data).
Table 8: Output Signal Reset State
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OX16C954 rev B
8
TRANSMITTER AND RECEIVER FIFOS
FCR[2]: Flush THR logic 0 No change. logic 1 Flushes the contents of the THR, in the same manner as FCR[1] does for the RHR.
Both the transmitter and receiver have associated holding registers (FIFOs), referred to as the transmitter holding register (THR) and receiver holding register (RHR) respectively. In normal operation, when the transmitter finishes transmitting a byte it will remove the next data from the top of the THR and proceed to transmit it. If the THR is empty, it will wait until data is written into it. If THR is empty and the last character being transmitted has been completed (i.e. the transmitter shift register is empty) the transmitter is said to be idle. Similarly, when the receiver finishes receiving a byte, it will transfer it to the bottom of the RHR. If the RHR is full, an overrun condition will occur (see section 9.3). Data is written into the bottom of the THR queue and read from the top of the RHR queue completely asynchronously to the operation of the transmitter and receiver. The size of the FIFOs is dependent on the setting of the FCR register. When in Byte mode, these FIFOs only accept one byte at a time before indicating that they are full; this is compatible with the 16C450. When in a FIFO mode, the size of the FIFOs is either 16 (compatible with the 16C550) or 128. Data written to the THR when it is full is lost. Data read from the RHR when it is empty is invalid. The empty or full status of the FIFOs are indicated in the Line Status Register `LSR' (see section 9.3). Interrupts are generated when the UART is ready for data transfer to/from the FIFOs. The number of items in each FIFO may also be read back from the transmitter FIFO level (TFL) and receiver FIFO level (RFL) registers (see section 15.2).
DMA Transfer Signalling:
FCR[3]: DMA signalling mode / Tx trigger level enable logic 0 DMA mode '0'. logic 1 DMA mode '1'.
Note: In DMA mode 0, the transmitter trigger level is ALWAYS set to 1, thus ignoring FCR[5:4] and TTL.
DMA Control signals can be generated using the TXRDY# and RXRDY# pins. Their operation is defined as follows: The TXRDY# pin has no hysteresis and is simply activated using a comparison operation. When the UART is in DMA mode 0 (or in Byte mode), the TXRDY# output pin is active (low) whenever any channels transmit FIFO (THR) is empty, otherwise it is inactive. When in DMA mode 1, the TXRDY# pin is inactive (high) when every channels transmit FIFO is full, otherwise it is active, signifying that one or more channels have room in their transmit FIFOs. The RXRDY# pin can operate with hysteresis. In DMA mode 0 (or in Byte mode), RXRDY# is only active (low) when one or more channels have data in their receiver FIFO. It is inactive therefore, when all channels receiver FIFOs are empty. When in DMA mode 1, RXRDY# operates as follows: 1. RXRDY# is set active when any channels receiver FIFO fill level has reached the receiver interrupt trigger level for that channel, or a time-out event has occurred (see section 10.3). It remains active until condition 2 (defined below) is met. RXRDY# is set inactive when every channels receiver has been emptied. It remains in this state until condition 1 (defined above) occurs again.
8.1
FIFO Control Register `FCR'
FCR[0]: Enable FIFO mode logic 0 Byte mode. logic 1 FIFO mode. This bit should be enabled before setting the FIFO trigger levels. FCR[1]: Flush RHR logic 0 No change. logic 1 Flushes the contents of the RHR This is only operative when already in a FIFO mode. The RHR is automatically flushed whenever changing between Byte mode and a FIFO mode. This bit will return to zero after clearing the FIFOs. Data Sheet Revision 1.0
2.
Note for the 80 pin TQFP package, individual channel TXRDY#, RXRDY# signals are also generated. FCR[5:4]: THR trigger level Generally in 450, 550, extended 550 and 950 modes these bits are unused (see section 5 for mode definition). In 650 mode they define the transmitter interrupt trigger levels and in 750 mode FCR[5] increase the FIFO size. Page 23
OXFORD SEMICONDUCTOR LTD.
450, 550 and extended 550 modes: The transmitter interrupt trigger levels are set to 1 and FCR[5:4] are ignored. 650 mode: In 650 mode the transmitter interrupt trigger levels can be set to the following values: FCR[5:4] 00 01 10 11 Transmit Interrupt Trigger level 16 32 64 112
OX16C954 rev B
950 mode: Setting ACR[5]=1 enables 950-mode trigger levels set using the TTL register (see section 15.4), FCR[5:4] are ignored. FCR[7:6]: RHR trigger level In 550, 450, 550, extended 550, 650 and 750 modes: The receiver FIFO trigger levels are defined using FCR[7:6]. The interrupt trigger level and upper flow control trigger level where appropriate are defined by L1 in the table below. L2 defines the lower flow control trigger level. Separate upper and lower flow control trigger levels introduce a hysteresis element in in-band and out-of-band flow control (see section 13). In Byte mode (450 mode) the trigger levels are all set to 1. FCR 550
FIFO Size 16
Table 9: Transmit Interrupt Trigger Levels These levels only apply when in Enhanced mode and in DMA mode 1(FCR[3] = 1), otherwise the trigger level is set to 1. A transmitter empty interrupt will be generated (if enabled) if the TFL falls below the trigger level. 750 Mode: In 750 compatible non-enhanced (EFR[4] = 0) mode, transmitter trigger level is set to 1, FCR[4] is unused and FCR[5] defines the FIFO depth as follows: FCR[5]=0 Transmitter and receiver FIFO size is 16 bytes. FCR[5]=1 Transmitter and receiver FIFO size is 128 bytes. In non-Enhanced mode and when FIFOSEL# pin is high, FCR[5] is writable only when LCR[7] is set. Note that in Enhanced mode, the FIFO size is increased to 128 bytes when FCR[0] is set.
Mode Ext. 550 / 750 L2 n/a n/a n/a n/a L1 1 32 64 112
FIFO Size 128
650
FIFO Size 128
00 01 10 11
L1 1 4 8 14
L2 1 1 1 1
L1 16 32 112 120
L2 1 16 32 112
Table 10: Compatible Receiver Trigger Levels 950 mode: In similar fashion to for transmitter trigger levels, setting ACR[5]=1 enables 950-mode receiver trigger levels. FCR[7:6] are ignored. A receiver data interrupt will be generated (if enabled) if the Receiver FIFO Level (`RFL') reaches the upper trigger level.
9
9.1
LINE CONTROL & STATUS
False Start Bit Detection
difference is that the received data does not get transferred to the RHR.
On the falling edge of a start bit, the receiver will wait for 1/2 bit and re-synchronise the receiver's sampling clock onto the centre of the start bit. The start bit is valid if the SIN line is still low at this mid-bit sample and the receiver will proceed to read in a data character. Verifying the start bit prevents noise generating spurious character generation. Once the first stop bit has been sampled, the received data is transferred to the RHR and the receiver will then wait for a low transition on SIN (signifying the next start bit). The receiver will continue receiving data even if the RHR is full or the receiver has been disabled (see section 15.3) in order to maintain framing synchronisation. The only Data Sheet Revision 1.0
9.2
Line Control Register `LCR'
The LCR specifies the data format that is common to both transmitter and receiver. Writing 0xBF to LCR enables access to the EFR, XON1, XOFF1, XON2 and XOFF2, DLL and DLM registers. This value (0xBF) corresponds to an unused data format. Writing the value 0xBF to LCR will set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the data format of the transmitter and receiver data is not affected. Write the desired LCR value to exit from this selection.
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OXFORD SEMICONDUCTOR LTD.
LCR[1:0]: Data length LCR[1:0] Determines the data length of serial characters. Note however, that these values are ignored in 9-bit data framing mode, i.e. when NMR[0] is set. LCR[1:0] 00 01 10 11 Data length 5 bits 6 bits 7 bits 8 bits
OX16C954 rev B
9.3
Line Status Register `LSR'
This register provides the status of data transfer to CPU. LSR[0]: RHR data available logic 0 RHR is empty: no data available logic 1 RHR is not empty: data is available to be read. LSR[1]: RHR overrun error logic 0 No overrun error. logic 1 Data was received when the RHR was full. An overrun error has occurred. The error is flagged when the data would normally have been transferred to the RHR. LSR[2]: Received data parity error logic 0 No parity error in normal mode or 9th bit of received data is `0' in 9-bit mode. logic 1 Data has been received that did not have correct parity in normal mode or 9th bit of received data is `1' in 9-bit mode. The flag will be set when the data item in error is at the top of the RHR and cleared following a read of the LSR. In 9bit mode LSR[2] is no longer a flag and corresponds to the 9th bit of the received data in RHR. LSR[3]: Received data framing error logic 0 No framing error. logic 1 Data has been received with an invalid stop bit. This status bit is set and cleared in the same manner as LSR[2]. When a framing error occurs, the UART will try to re-synchronise by assuming that the error was due to sampling the start bit of the next data item. LSR[4]: Received break error logic 0 No receiver break error. logic 1 The receiver received a break. A break condition occurs when the SIN line goes low (normally signifying a start bit) and stays low throughout the start, data, parity and first stop bit. (Note that the SIN line is sampled at the bit rate). One zero character with associated break flag set will be transferred to the RHR and the receiver will then wait until the SIN line returns high. The LSR[4] break flag will be set when this data item gets to the top of the RHR and it is cleared following a read of the LSR. LSR[5]: THR empty logic 0 Transmitter FIFO (THR) is not empty. logic 1 Transmitter FIFO (THR) is empty.
Table 11: LCR Data Length Configuration LCR[2]: Number of stop bits LCR[2] defines the number of stop bits per serial character. LCR[2] 0 1 1 Data length 5,6,7,8 5 6,7,8 No. stop bits 1 1.5 2
Table 12: LCR Stop Bit Number Configuration LCR[5:3]: Parity type The selected parity type will be generated during transmission and checked by the receiver, which may produce a parity error as a result. In 9-bit mode parity is disabled and LCR[5:3] is ignored. LCR[5:3] xx0 001 011 101 111 Parity type No parity bit Odd parity bit Even parity bit Parity bit forced to 1 Parity bit forced to 0
Table 13: LCR Parity Configuration LCR[6]: Transmission break logic 0 Break transmission disabled. logic 1 Forces the transmitter data output SOUT low to alert the communication terminal, or send zeros in IrDA mode. It is the responsibility of the software driver to ensure that the break duration is longer than the character period for it to be recognised remotely as a break rather than data. LCR[7]: Divisor latch enable logic 0 Access to DLL and DLM registers disabled. logic 1 Access to DLL and DLM registers enabled.
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LSR[6]: Transmitter and THR empty logic 0 The transmitter is not idle logic 1 THR is empty and the transmitter has completed the character in shift register and is in idle mode. (I.e. set whenever the transmitter shift register and the THR are both empty.) LSR[7]: Receiver data error logic 0 Either there are no receiver data errors in the FIFO or it was cleared by an earlier read of LSR.
OX16C954 rev B
logic 1 At least one parity error, framing error or break indication in the FIFO. In 450 mode LSR[7] is permanently cleared, otherwise this bit will be set when an erroneous character is transferred from the receiver to the RHR. It is cleared when the LSR is read. Note that in 16C550 this bit is only cleared when all of the erroneous data are removed from the FIFO. In 9-bit data framing mode parity is permanently disabled, so this bit is not affected by LSR[2].
10 INTERRUPTS & SLEEP MODE
In Intel mode, the serial channel interrupts are asserted on the respective INT pin. When INTSEL# is high the INT pin is permanently enabled and MCR[3] is ignored. When INTSEL# is low or unconnected, the tri-state control of INT is controlled by MCR[3] (enabled when MCR[3] is set, highimpedance state when MCR[3] is cleared). In Motorola mode, all channel interrupts are ORed together and asserted on the IRQ# pin. The INTSEL# pin has no effect in this mode. The tri-state control of each channels interrupt is controlled by MCR[3]. Any non-tristated channel interrupt causes IRQ# to be asserted. In 9-bit mode (i.e. when NMR[0] is set), reception of a character with the address-bit (i.e. 9th bit) set can generate a level 1 interrupt if IER[2] is set. IER[3]: Modem status interrupt mask logic 0 Disable the modem status interrupt. logic 1 Enable the modem status interrupt. IER[4]: Sleep mode logic 0 Disable sleep mode. logic 1 Enable sleep mode whereby the internal clock of the channel is switched off. Sleep mode is described in section 10.4. IER[5]: Special character interrupt mask or alternate sleep mode 9-bit data framing mode: logic 0 Disable the received special character interrupt. logic 1 Enable the received special character interrupt. In 9-bit data mode, The receiver can detect up to four special characters programmed in the Special Character Registers (see map on page 19). When IER[5] is set, a level 5 interrupt is asserted when the receiver character matches one of the values programmed. 650/950 modes (non-9-bit data framing): logic 0 Disable the special character receive interrupt. logic 1 Enable the special character receive interrupt. In 16C650 compatible mode when the device is in Enhanced mode (EFR[4]=1), this bit enables the detection of special characters. It enables both the detection of XOFF characters (when in-band flow control is enabled via EFR[3:0]) and the detection of the XOFF2 special character (when enabled via EFR[5]).
10.1 Interrupt Enable Register `IER'
Serial channel interrupts are enabled using the Interrupt Enable Register (`IER'). IER[0]: Receiver data available interrupt mask logic 0 Disable the receiver ready interrupt. logic 1 Enable the receiver ready interrupt. IER[1]: Transmitter empty interrupt mask logic 0 Disable the transmitter empty interrupt. logic 1 Enable the transmitter empty interrupt. IER[2]: Receiver status interrupt Normal mode: logic 0 Disable the receiver status interrupt. logic 1 Enable the receiver status interrupt. 9-bit data mode: logic 0 Disable receiver status and address bit interrupt. logic 1 Enable receiver status and address bit interrupt.
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750 mode (non-9-bit data framing): logic 0 Disable alternate sleep mode. logic 1 Enable alternate sleep mode whereby the internal clock of the channel is switched off. In 16C750 compatible mode (i.e. non-Enhanced mode), this bit is used an alternate sleep mode and has the same effect as IER[4]. (See section 10.4). IER[6]: RTS interrupt mask logic 0 Disable the RTS interrupt. logic 1 Enable the RTS interrupt. This enable is only operative in Enhanced mode (EFR[4]=1). In non-Enhanced mode, RTS interrupt is permanently enabled IER[7]: CTS interrupt mask logic 0 Disable the CTS interrupt. logic 1 Enable the CTS interrupt. This enable is only operative in Enhanced mode (EFR[4]=1). In non-Enhanced mode, CTS interrupt is permanently enabled.
OX16C954 rev B
10.3 Interrupt Description
Receiver status error interrupt (ISR[5:0]='000110'): Normal (non-9-bit) mode: This interrupt is active whenever any of LSR[1], LSR[2], LSR[3] or LSR[4] are set. These flags are cleared following a read of the LSR. This interrupt is masked with IER[2]. 9-bit mode: This interrupt is active whenever any of LSR[1], LSR[2], LSR[3] or LSR[4] are set. The receiver error interrupt due to LSR[1], LSR[3] and LSR[4] is masked with IER[3]. The `address-bit' received interrupt is masked with NMR[1]. The software driver can differentiate between receiver status error and received address-bit (9th data bit) interrupt by examining LSR[1] and LSR[7]. In 9-bit mode LSR[7] is only set when LSR[3] or LSR[4] is set and it is not affected by LSR[2] (i.e. 9th data bit). Receiver data available interrupt (ISR[5:0]='000100'): This interrupt is active whenever the receiver FIFO level is above the interrupt trigger level. Receiver time-out interrupt (ISR[5:0]='001100'): A receiver time-out event, which may cause an interrupt, will occur when all of the following conditions are true: * The UART is in a FIFO mode * There is data in the RHR. * There has been no read of the RHR for a period of time greater than the time-out period. * There has been no new data written into the RHR for a period of time greater than the time-out period. The time-out period is four times the character period (including start and stop bits) measured from the centre of the first stop bit of the last data item received. Reading the first data item in RHR clears this interrupt.
Level 1:
Level 2a:
10.2 Interrupt Status Register `ISR'
The source of the highest priority interrupt pending is indicated by the contents of the Interrupt Status Register `ISR'. There are nine sources of interrupt at six levels of priority (1 is the highest) as shown in Table 14. Level 1 2a 2b 3 4 52 Interrupt source No interrupt pending Receiver status error or Address-bit detected in 9-bit mode Receiver data available Receiver time-out Transmitter THR empty Modem status change In-band flow control XOFF or Special character (XOFF2) or Special character 1, 2, 3 or 4 or bit 9 set in 9-bit mode CTS or RTS change of state
1
Level 2b:
ISR[5:0]
see note 3
000001 000110 000100 001100 000010 000000 010000
Level 3:
100000
6
2
Table 14: Interrupt Status Identification Codes
Note1: ISR[0] indicates whether any interrupts are pending. Note2: Interrupts of priority levels 5 and 6 cannot occur unless the UART is in Enhanced mode. Note3: ISR[5] is only used in 650 & 950 modes. In 750 mode, it is `0' when FIFO size is 16 and `1' when FIFO size is 128. In all other modes it is permanently set to 0
Transmitter empty interrupt (ISR[5:0]='000010'): This interrupt is set when the transmit FIFO level falls below the trigger level. It is cleared on an ISR read of a level 3 interrupt or by writing more data to the THR so that the trigger level is exceeded. Note that when 16C950 mode trigger levels are enabled (ACR[5]=1) and the transmitter trigger level of zero is selected (TTL=0x00), a transmitter empty interrupt will only be asserted when both the transmitter FIFO and transmitter shift register are empty and the SOUT line has returned to idle marking state. Page 27
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Modem change interrupt (ISR[5:0]='000000'): This interrupt is set by a modem change flag (MSR[0], MSR[1], MSR[2] or MSR[3]) becoming active due to changes in the input modem lines. This interrupt is cleared following a read of the MSR. Receiver in-band flow control (XOFF) detect interrupt, Receiver special character (XOFF2) detect interrupt, Receiver special character 1, 2, 3 or 4 interrupt or 9th Bit set interrupt in 9-bit mode (ISR[5:0]='010000'): A level 5 interrupt can only occur in Enhanced-mode when any of the following conditions are met: * A valid XOFF character is received while in-band flow control is enabled. * A received character matches XOFF2 while special character detection is enabled, i.e. EFR[5]=1. * A received character matches special character 1, 2, 3 or 4 in 9-bit mode (see section 15.9). It is cleared on an ISR read of a level 5 interrupt.
10.4 Sleep Mode
For a channel to go into sleep mode, all of the following conditions must be met: * * * * * * * * Sleep mode enabled (IER[4]=1 in 650/950 modes, or IER[5]=1 in 750 mode): The transmitter is idle, i.e. the transmitter shift register and FIFO are both empty. SIN is high. The receiver is idle. The receiver FIFO is empty (LSR[0]=0). The UART is not in loopback mode (MCR[4]=0). Changes on modem input lines have been acknowledged (i.e. MSR[3:0]=0000). No interrupts are pending.
Level 5:
Level 6:
CTS or RTS changed interrupt (ISR[5:0]='100000'): This interrupt is set whenever any of the CTS# or RTS# pins changes state from low to high. It is cleared on an ISR read of a level 6 interrupt.
A read of IER[4] (or IER[5] if a 1 was written to that bit instead) shows whether the power-down request was successful. The UART will fully retain its programmed state whilst in power-down mode. The channel will automatically exit power-down mode when any of the conditions 1 to 7 becomes false. It may be woken manually by clearing IER[4] (or IER[5] if the alternate sleep mode is enabled). Sleep mode operation is not available in IrDA mode.
11 MODEM INTERFACE
11.1 Modem Control Register `MCR'
MCR[0]: DTR logic 0 Force DTR# output to inactive (high). logic 1 Force DTR# output to active (low). Note that DTR# can be used for automatic out-of-band flow control when enabled using ACR[4:3] (see section 15.3). MCR[1]: RTS logic 0 Force RTS# output to inactive (high). logic 1 Force RTS# output to active (low). Note that RTS# can be used for automatic out-of-band flow control when enabled using EFR[6] (see section 13.4). MCR[2]: OUT1 Writing this bit will have no affect on operation. Reading this bit will return the last value written. This bit is only used for test purposes in local loop-back mode (MCR[4] = `1'). MCR[3]: OUT2 / External interrupt enable logic 0 The interrupt pin is in high-impedance state and will never be asserted logic 1 The interrupt pin is enabled and will be asserted when interrupts occur. Used for test in local loop-back mode(MCR[4] = `1')
Note: In Intel mode, the INTSEL# pin must also be low. When INTSEL# is high, interrupts are permanently enabled in this mode.
MCR[4]: Loopback mode logic 0 Normal operating mode. logic 1 Enable local loop-back mode (diagnostics). In local loop-back mode, the transmitter output (SOUT) and the two modem outputs (DTR#, RTS#) are set in-active (high), and the receiver inputs SIN, CTS#, DSR#, DCD#, and RI# are all disabled. Internally the transmitter output is connected to the receiver input and DTR#, RTS#, OUT1# and OUT2# are connected to modem status inputs DSR#, CTS#, RI# and DCD# respectively. Page 28
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In this mode, the receiver and transmitter interrupts are fully operational. The modem control interrupts are also operational, but the interrupt sources are now the lower four bits of the Modem Control Register instead of the four modem status inputs. The interrupts are still controlled by the IER. MCR[5]: Enable XON-Any in Enhanced mode or enable out-of-band flow control in non-Enhanced mode 650/950 (enhanced) modes: logic 0 XON-Any is disabled. logic 1 XON-Any is enabled. In enhanced mode (EFR[4]=1), this bit enables the XonAny operation. When Xon-Any is enabled, any received data will be accepted as a valid XON (see in-band flow control, section 13.3). 750 (normal) mode: logic 0 CTS/RTS flow control disabled. logic 1 CTS/RTS flow control enabled. In non-enhanced mode, this bit enables the CTS/RTS outof-band flow control. MCR[6]: IrDA mode logic 0 Standard serial receiver and transmitter data format. logic 1 Data will be transmitted and received in IrDA format. This function is only available in Enhanced mode. It requires a 16x clock to function correctly. MCR[7]: Baud rate prescaler select logic 0 Normal (divide by 1) baud rate generator prescaler selected. logic 1 Divide-by-"M+N/8" baud rate generator prescaler selected. where M & N are programmed in CPR (ICR offset 0x01). After a hardware reset, CPR defaults to 0x20 (divide-by-4) and MCR[7] is reset. User writes to this flag will only take effect in Enhanced mode. See section 13.1.
OX16C954 rev B
11.2 Modem Status Register `MSR'
MSR[0]: Delta CTS# Indicates that the CTS# input has changed since the last time the MSR was read. MSR[1]: Delta DSR# Indicates that the DSR# input has changed since the last time the MSR was read. MSR[2]: Trailing edge RI# Indicates that the RI# input has changed from low to high since the last time the MSR was read. MSR[3]: Delta DCD# Indicates that the DCD# input has changed since the last time the MSR was read. MSR[4]: CTS This bit is the complement of the CTS# input. It is equivalent to RTS (MCR[1]) in internal loop-back mode. MSR[5]: DSR This bit is the complement of the DSR# input. It is equivalent to DTR (MCR[0]) in internal loop-back mode. MSR[6]: RI This bit is the complement of the RI# input. In internal loopback mode it is equivalent to the internal OUT1. MSR[7]: DCD This bit is the complement of the DCD# input. In internal loop-back mode it is equivalent to the internal OUT2.
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12 OTHER STANDARD REGISTERS
12.1 Divisor Latch Registers `DLL & DLM'
The divisor latch registers are used to program the baud rate divisor. This is a value between 1 and 65535 by which the input clock is divided by in order to generate serial baud rates. After a hardware reset, the baud rate used by the transmitter and receiver is given by:
12.2 Scratch Pad Register `SPR'
The scratch pad register does not affect operation of the rest of the UART in any way and can be used for temporary data storage. The register may also be used to define an offset value to access the registers in the Indexed Control Register set. For more information on Indexed Control registers see Table 7and section 15.
Baudrate =
InputClock 16 * Divisor
Where divisor is given by DLL + ( 256 x DLM ). More flexible baud rate generation options are also available. See section 14 for full details.
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13 AUTOMATIC FLOW CONTROL
Automatic in-band flow control, automatic out-of-band flow control and special character detection features can be used when in Enhanced mode and are software compatible with the 16C654. Alternatively, 750-compatible automatic out-of-band flow control can be enabled when in nonEnhanced mode. In 950 mode, in-band and out-of-band flow controls are compatible with 16C654 with the addition of fully programmable flow control thresholds. EFR[3:2]: In-band transmit flow control mode When in-band transmit flow control is enabled, an XON/XOFF character is inserted into the data stream whenever the RFL passes the upper trigger level and falls below the lower trigger level respectively. For automatic in-band flow control, bit 4 of EFR must be set. The combinations of software transmit flow control can then be selected by programming EFR[3:2] as follows: logic [00] In-band transmit flow control is disabled. logic [01] Single character in-band transmit flow control enabled, using XON2 as the XON character and XOFF2 as the XOFF character. logic [10] Single character in-band transmit flow control enabled, using XON1 as the XON character and XOFF1 as the XOFF character. logic[11] The value EFR[3:2] = "11" is reserved for future use and should not be used EFR[4]: Enhanced mode logic 0 Non-Enhanced mode. Disables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 5-7 and inband flow control. Whenever this bit is cleared, the setting of other bits of EFR are ignored. logic 1 Enhanced mode. Enables the Enhanced Mode functions. These functions include enabling IER bits 4-7, FCR bits 4-5, MCR bits 5-7. For in-band flow control the software driver must set this bit first. If this bit is set, out-of-band flow control is configured with EFR bits 6-7, otherwise out-of-band flow control is compatible with 16C750. EFR[5]: Enable special character detection logic 0 Special character detection is disabled. logic 1 While in Enhanced mode (EFR[4]=1), the UART compares the incoming receiver data with the XOFF2 value. Upon a correct match, the received data will be transferred to the RHR and a level 5 interrupt (XOFF or special character) will be asserted if level 5 interrupts are enabled (IER[5] set to 1).
13.1 Enhanced Features Register `EFR'
Writing 0xBF to LCR enables access to the EFR and other Enhanced mode registers. This value corresponds to an unused data format. Writing 0xBF to LCR will set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the data format of the transmitter and receiver data is not affected. Write the desired LCR value to exit from this selection. Note: In-band transmit and receive flow control is disabled in 9-bit mode. EFR[1:0]: In-band receive flow control mode When in-band receive flow control is enabled, the UART compares the received data with the programmed XOFF character. When this occurs, the UART will disable transmission as soon as any current character transmission is complete. The UART then compares the received data with the programmed XON character. When a match occurs, the UART will re-enable transmission (see section 15.6). For automatic in-band flow control, bit 4 of EFR must be set. The combinations of software receive flow control can be selected by programming EFR[1:0] as follows: logic [00] In-band receive flow control is disabled. logic [01] Single character in-band receive flow control enabled, recognising XON2 as the XON character and XOFF2 as the XOFF character. logic [10] Single character in-band receive flow control enabled, recognising XON1 as the XON character and XOFF1 as the XOFF character. logic [11] The behaviour of the receive flow control is dependent on the configuration of EFR[3:2]. Single character in-band receive flow control is enabled, accepting XON1 or XON2 as valid XON characters and XOFF1 or XOFF2 as valid XOFF characters when EFR[3:2] = "01" or "10". EFR[1:0] should not be set to "11" when EFR[3:2] is `00'.
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EFR[6]: Enable automatic RTS flow control. logic 0 RTS flow control is disabled (default). logic 1 RTS flow control is enabled in Enhanced mode (i.e. EFR[4] = 1), where the RTS# pin will be forced inactive high if the RFL reaches the upper flow control threshold. This will be released when the RFL drops below the lower threshold. 650 and 950-mode drivers should use this bit to enable RTS flow control. 750 mode drivers should use MCR[5]. EFR[7]: Enable automatic CTS flow control. logic 0 CTS flow control is disabled (default). logic 1 CTS flow control is enabled in Enhanced mode (i.e. EFR[4] = 1), where the data transmission is prevented whenever the CTS# pin is held inactive high. 650 and 950-mode drivers should use this bit to enable CTS flow control. 750 mode drivers should use MCR[5].
OX16C954 rev B
When the 'XON Any' flag (MCR[5]) is set, any received character is accepted as a valid XON condition and the transmitter will be re-enabled. The received data will be transferred to the RHR. When in-band transmit flow control is enabled, the RFL will be sampled whenever the transmitter is idle (briefly, between characters, or when the THR is empty) and an XON/XOFF character will be inserted into the data stream if needed. Initially, remote transmissions are enabled and hence ASR[1] is clear. If ASR[1] is clear and the RFL has passed the upper trigger level (i.e. is above the trigger level), XOFF will be sent and ASR[1] will be set. If ASR[1] is set and the RFL falls below the lower trigger level, XON will be sent and ASR[1] will be cleared. If transmit flow control is disabled after an XOFF has been sent, an XON will be sent automatically.
13.4 Automatic Out-of-band Flow Control 13.2 Special Character Detection
In Enhanced mode (EFR[4]=1), when special character detection is enabled (EFR[5]=1) and the receiver matches received data with XOFF2, the 'received special character' flag ASR[4] will be set and a level 5 interrupt is asserted, if enabled by IER[5]. This flag will be cleared following a read of ASR. The received status (i.e. parity and framing) of special characters does not have to be valid for these characters to be accepted as valid matches. Automatic RTS/CTS flow control is selected by different means, depending on whether the UART is in Enhanced or non-Enhanced mode. When in non-Enhanced mode, MCR[5] enables both RTS and CTS flow control. When in Enhanced mode, EFR[6] enables automatic RTS flow control and EFR[7] enables automatic CTS flow control. This allows software compatibility with both 16C650 and 16C750 drivers. When automatic CTS flow control is enabled and the CTS# input becomes active, the UART will disable transmission as soon as any current character transmission is complete. Transmission is resumed whenever the CTS# input becomes inactive. When automatic RTS flow control is enabled, the RTS# pin will be forced inactive when the RFL reaches the upper trigger level and will return to active when the RFL falls below the lower trigger level. The automatic RTS# flow control is ANDed with MCR[1] and hence is only operational when MCR[1]=1. This allows the software driver to override the automatic flow control and disable the remote transmitter regardless by setting MCR[1]=0 at any time. Automatic DTR/DSR flow control behaves in the same manner as RTS/CTS flow control but is enabled by ACR[3:2], regardless of whether or not the UART is in Enhanced mode.
13.3 Automatic In-band Flow Control
When in-band receive flow control is enabled, the UART will compare the received data with XOFF1 or XOFF2 characters to detect an XOFF condition. When this occurs, the UART will disable transmission as soon as any current character transmission is complete. Status bits ISR[4] and ASR[0] will be set. A level 5 interrupt will occur (if enabled by IER[5]). The UART will then compare all received data with XON1 or XON2 characters to detect an XON condition. When this occurs, the UART will re-enable transmission and status bits ISR[4] and ASR[0] will be cleared. Any valid XON/XOFF characters will not be written into the RHR. An exception to this rule occurs if special character detection is enabled and an XOFF2 character is received that is a valid XOFF. In this instance, the character will be written into the RHR. The received status (i.e. parity and framing) of XON/XOFF characters does not have to be valid for these characters to be accepted as valid matches.
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14 BAUD RATE GENERATION
14.1 General Operation
The UART contains a programmable baud rate generator that is capable of taking any clock input from 1.8432MHz to 60MHz (at 5V) and dividing it by any 16-bit divisor number from 1 to 65535 written into the DLM (MSB) and DLL (LSB) registers. In addition to this, a clock prescaler register is provided which can further divide the clock by values in the range 1.0 to 31.875 in steps of 0.125. Also, a further feature is the Times Clock Register `TCR' which allows the sampling clock to be set to any value between 4 and 16. These clock options allow for highly flexible baud rate generation capabilities from almost any input clock frequency (up to 60MHz). The actual transmitter and receiver baud rate is calculated as follows: DLM:DLL Divisor Word 0x0900 0x0300 0x0180 0x00C0 0x0060 0x0030 0x0018 0x000C 0x0006 0x0004 0x0003 0x0002 0x0001 Baud Rate (bits per second) 50 110 300 600 1,200 2,400 4,800 9,600 19,200 28,800 38,400 57,600 115,200
BaudRate =
InputClock SC * Divisor * prescaler
Table 15: Standard PC COM Port Baud Rate Divisors (assuming a 1.8432MHz crystal)
Where: SC = Sample clock values defined in TCR[3:0] Divisor = DLL + ( 256 x DLM ) Prescaler = 1 when MCR[7] = `0' else: = M + ( N / 8 ) where: M = CPR[7:3] (Integer part - 1 to 31) N = CPR[2:0] (Fractional part - 0.000 to 0.875 ) See the next section for a discussion of the clock prescaler and times clock register. After a hardware reset, the prescaler is bypassed (set to 1) and TCR is set to 0x00 (i.e. SC = 16). Assuming this default configuration, the following table gives the divisors required to be programmed into the DLL and DLM registers in order to obtain various standard baud rates:
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14.2 Clock Prescaler Register `CPR'
The CPR register is located at offset 0x01 of the ICR The prescaler divides the system clock by any value in the range of 1 to "31 7/8" in steps of 1/8. The divisor takes the form "M+N/8", where M is the 5 bit value defined in CPR[7:3] and N is the 3 bit value defined in CPR[2:0]. The prescaler is by-passed and a prescaler value of `1' is selected by default when MCR[7] = 0. MCR[7] is set to the complement of CLKSEL pin after a hardware reset but may be overwritten by software. Note however that since access to MCR[7] is restricted to Enhanced mode only, EFR[4] should first be set and then MCR[7] set or cleared as required. If CLKSEL is connected to ground or MCR[7] is set by software, the internal clock prescaler is enabled. Upon a hardware reset, CPR defaults to 0x20 (division-by4). Compatibility with existing 16C550 baud rate divisors is maintained using either a 1.8432MHz clock with CLKSEL pin connected to VDD, or a 7.372MHz clock with CLKSEL connected to ground. In the latter case, clearing MCR[7] would bypass the prescaler and hence quadruple all selected baud rates (providing a maximum of 460.8kbps as opposed to 115.2kbps) For higher baud rates use a higher frequency clock, e.g. 14.7456MHz, 18.432MHz, 32MHz, 40MHz or 60.0MHz. The flexible prescaler allows system designers to generate popular baud rates using clocks that are not integer multiples of the required rate. When using a non-standard clock frequency, compatibility with existing 16C550 software drivers may be maintained with a minor software patch to program the on-board prescaler to divide the high frequency clock down to 1.8432MHz. Table 17 on the following page gives the prescaler values required to operate the UARTs at compatible baud rates with various different crystal frequencies. Also given is the maximum available baud rates in TCR = 16 and TCR = 4 modes with CPR = 1.
14.3 Times Clock Register `TCR'
The TCR register is located at offset 0x02 of the ICR The 16C550 and other compatible devices such as 16C650 and 16C750 use a 16 times (16x) over-sampling channel clock. The 16x over-sampling clock means that the channel clock runs at 16 times the selected serial bit rate. It limits the highest baud rate to 1/16 of the system clock when using a divisor latch value of unity. However, each UART of the OX16C954 is designed in a manner to enable it to accept other multiplications of the bit rate clock. It can use values from 4x to 16x clock as programmed in the TCR as long as the clock (oscillator) frequency error, stability and jitter are within reasonable parameters. Upon hardware reset the TCR is reset to 0x00 which means that a 16x clock will be used, for compatibility with the 16C550 and compatibles. The maximum baud-rates available for various system clock frequencies at all of the allowable values of TCR are indicated in Table 18 on the following page. These are the values in bits-per-second (bps) that are obtained if the divisor latch = 0x01 and the Prescaler is set to 1. The OX16C954 has the facility to operate at baud-rates up to 15 Mbps at 5V. The table below indicates how the value in the register corresponds to the number of clock cycles per bit. TCR[3:0] is used to program the clock. TCR[7:4] are unused and will return "0000" if read. TCR[3:0] 0000 to 0011 0100 to 1111 Clock cycles per bit 16 4-15
Table 16: TCR Sample Clock Configuration The use of TCR does not require the device to be in 650 or 950 mode although only drivers that have been written to take advantage of the 950 mode features will be able to access this register. Writing 0x01 to the TCR will not switch the device into 1x isochronous mode, this is explained in the following section. (TCR has no effect in isochronous mode). If 0x01, 0x10 or 0x11 is written to TCR the device will operate in 16x mode. Reading TCR will always return the last value that was written to it irrespective of mode of operation.
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Clock Frequency (MHz) 1.8432 7.3728 14.7456 18.432 32.000 33.000 40.000 50.000 60.000
CPR value 0x08 (1) 0x20 (4) 0x40 (8) 0x50 (10) 0x8B (17.375) 0x8F (17.875) 0xAE (21.75) 0xD9 (27.125) 0xFF (31.875)
Effective crystal frequency 1.8432 1.8432 1.8432 1.8432 1.8417 1.8462 1.8391 1.8433 1.8824
Error from 1.8432MHz (%) 0.00 0.00 0.00 0.00 0.08 0.16 0.22 0.01 2.13
Max. Baud rate with CPR = 1, TCR = 16 115,200 460,800 921,600 1,152,000 2,000,000 2,062,500 2,500,000 3,125,000 3,750,000
Max. Baud rate with CPR = 1, TCR = 4 460,800 1,843,200 3,686,400 4,608,000 8,000,000 8,250,000 10,000,000 12,500,000 15,000,000
Table 17: Example clock options and their associated maximum baud rates
Sampling TCR Clock Value
System Clock (MHz) 1.8432 7.372 14.7456 18.432 32 40 50 60
16 15 14 13 12 11 10 9 8 7 6 5 4
0x00 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04
115,200 122,880 131,657 141,785 153,600 167,564 184,320 204,800 230,400 263,314 307,200 368,640 460,800
460,750 491,467 526,571 567,077 614,333 670,182 737,200 819,111 921,500 1,053,143 1,228,667 1,474,400 1,843,000
921,600 983,040 1,053,257 1,134,277 1,228,800 1,340,509 1,474,560 1,638,400 1,843,200 2,106,514 2,457,600 2,949,120 3,686,400
1.152M 1,228,800 1,316,571 1,417,846 1,536,000 1,675,636 1,843,200 2,048,000 2,304,000 2,633,143 3,072,000 3,686,400 4,608,000
2.00M 2,133,333 2,285,714 2,461,538 2,666,667 2,909,091 3.20M 3,555,556 4.00M 4,571,429 5,333,333 6.40M 8.00M
2.50M 2,666,667 2,857,143 3,076,923 3,333,333 3,636,364 4.00M 4,444,444 5.00M 5,714,286 6,666,667 8.00M 10.00M
3.125M 3,333,333 3,571,429 3,846,154 4,166,667 4,545,455 5.00M 5,555,556 6.25M 7,142,857 8,333,333 10.00M 12.50M
3.75M 4.00M 4,285,714 4,615,384 5.00M 5,454545 6.00M 6,666,667 7.50M 8,571428 10.00M 12.00M 15.00M
Table 18: Maximum Baud Rates Available at all `TCR' Sampling Clock Values
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framing is maintained using start, parity and stop-bits. However serial transmission and reception is synchronised to the 1x clock. In this mode asynchronous data may be transmitted at baud rates up to 60Mbps. The local 1x clock source can be asserted on the DTR# pin. Note that line drivers need to be capable of transmission at data rates twice the system clock used (as one cycle of the system clock corresponds to 1 bit of serial data). Also note that enabling modem interrupts is illegal in isochronous mode, as the clock signal will cause a continuous change to the modem status (unless masked in MDM register, see section 15.10).
14.4 Input Clock Options
A system clock must be applied to XTLI pin on the device. The speed of this clock determines the maximum baud rate at which the device can receive and transmit serial data. This maximum is equal to one sixteenth of the frequency of the system clock (Increasing to one quarter of this value if TCR=4 is used) The industry standard system clock for PC COM ports is 1.8432 MHz, limiting the maximum baud rate to 115.2 Kbps. The OX16C95x UARTs support system clocks up to 60MHz (at 5V) and its flexible baud rate generation hardware means that almost any frequency can be optionally scaled down for compatibility with standard devices. Designers have the option of using either TTL clock modules or crystal oscillator circuits for system clock input, with minimal additional components. The following two sections describe how each can be connected.
14.7 Crystal Oscillator Circuit
The OX16C954 may be clocked by a crystal connected to XTLI and XTLO or directly from a clock source connected to the XTLI pin (or CLKSEL if selected by software). The circuit required to use the on-chip oscillator is shown in Figure 3.
14.5 TTL Clock Mode
Using a TTL module for the system clock simply requires the module to be supplied with power and GND connections. The clock output can then be connected directly to XTLI. XTLO should be left unconnected.
XTLO R2 R1 C1
XTLI C2
VDD
CLOCK
Figure 3: Crystal Oscillator Circuit
XTLI
Figure 2: TTL Clock Module Connectivity
14.6 External 1x Clock Mode
The transmitter and receiver can accept an external clock applied to the RI# and DSR# pins respectively. The clock options are selected using the CKS register (see section 15.8). The transmitter and receiver may be configured to operate in 1x (i.e. Isochronous mode) by setting CKS[7] and CKS[3], respectively. In Isochronous mode, transmitter or receiver will use the 1x clock (usually, but not necessarily, an external source) where asynchronous
Frequency Range (MHz) 1.8432 - 8 8-60
C1 (pF) 68 33-68
C2 (pF) 22 33 - 68
R1 ( ) 220k 220k-2M2
R2 ( ) 470R 470R
Table 19: Component values Note: For better stability use a smaller value of R1. Increase R1 to reduce power consumption. The total capacitive load (C1 in series with C2) should be that specified by the crystal manufacturer (nominally 16pF).
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15 ADDITIONAL FEATURES
15.1 Additional Status Register `ASR'
ASR[0]: Transmitter disabled logic 0 The transmitter is not disabled by in-band flow control. logic 1 The receiver has detected an XOFF, and has disabled the transmitter. This bit is cleared after a hardware reset or channel software reset. The software driver may write a 0 to this bit to re-enable the transmitter if it was disabled by in-band flow control. Writing a 1 to this bit has no effect. ASR[1]: Remote transmitter disabled logic 0 The remote transmitter is not disabled by inband flow control. logic 1 The transmitter has sent an XOFF character, to disable the remote transmitter (cleared when subsequent XON is sent). This bit is cleared after a hardware reset or channel software reset. The software driver may write a 0 to this bit to re-enable the remote transmitter (an XON is transmitted). Note: writing a 1 to this bit has no effect. Note: The remaining bits (ASR[7:2]) are read-only. ASR[2]: RTS This is the complement of the actual state of the RTS# pin when the device is not in loopback mode. The driver software can determine if the remote transmitter is disabled by RTS# out-of-band flow control by reading this bit. In loopback mode this bit reflects the flow control status rather than the pin's actual state. ASR[3]: DTR This is the complement of the actual state of the DTR# pin when the device is not in loopback mode. The driver software can determine if the remote transmitter is disabled by DTR# out-of-band flow control by reading this bit. In loopback mode this bit reflects the flow control status rather than the pin's actual state. ASR[4]: Special character detected logic 0 No special character has been detected. logic 1 A special character has been received and is stored in the RHR. This can be used to determine whether a level 5 interrupt was caused by receiving a special character rather than an XOFF. The flag is cleared following the read of the ASR. Data Sheet Revision 1.0 ASR[5]: FIFOSEL This bit reflects the unlatched state of the FIFOSEL pin. ASR[6]: FIFO size logic 0 FIFOs are 16 deep if FCR[0] = 1. logic 1 FIFOs are 128 deep if FCR[0] = 1. Note: If FCR[0] = 0, the FIFOs are 1 deep. ASR[7]: Transmitter Idle logic 0 Transmitter is transmitting. logic 1 Transmitter is idle. This bit reflects the state of the internal transmitter. It is set when both the transmitter FIFO and shift register are empty.
15.2 FIFO Fill levels `TFL & RFL'
The number of characters stored in the THR and RHR can be determined by reading the TFL and RFL registers respectively. As the UART clock is asynchronous with respect to the processor, it is possible for the levels to change during a read of these FIFO levels. It is therefore recommended that the levels are read twice and compared to check that the values obtained are valid. The values should be interpreted as follows: 1. 2. The number of characters in the THR is no greater than the value read back from TFL. The number of characters in the RHR is no less than the value read back from RFL.
15.3 Additional Control Register `ACR'
The ACR register is located at offset 0x00 of the ICR ACR[0]: Receiver disable logic 0 The receiver is enabled, receiving data and storing it in the RHR. logic 1 The receiver is disabled. The receiver continues to operate as normal to maintain the framing synchronisation with the receive data stream but received data is not stored into the RHR. In-band flow control characters continue to be detected and acted upon. Special characters will not be detected. Changes to this bit will only be recognised following the completion of any data reception pending.
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ACR[1]: Transmitter disable logic 0 The transmitter is enabled, transmitting any data in the THR. logic 1 The transmitter is disabled. Any data in the THR is not transmitted but is held. However, inband flow control characters may still be transmitted. Changes to this bit will only be recognised following the completion of any data transmission pending. ACR[2]: Enable automatic DSR flow control logic 0 Normal. The state of the DSR# line does not affect the flow control. logic 1 Data transmission is prevented whenever the DSR# pin is held inactive high. This bit provides another automatic out-of-band flow control facility using the DSR# line. ACR[4:3]: DTR# line configuration When bits 4 or 5 of CKS (offset 0x03 of ICR) are set, the transmitter 1x clock or the output of the baud rate generator (Nx clock) are asserted on the DTR# pin, otherwise the DTR# pin is defined as follows: logic [00] DTR# is compatible with 16C450, 16C550, 16C650 and 16C750 (i.e. normal). logic [01] DTR# pin is used for out-of-band flow control. It will be forced inactive high if the Receiver FIFO Level (`RFL') reaches the upper flow control threshold. DTR# line will be reactivated (=0) when the RFL drops below the lower threshold (see FCL & FCH). logic [10] DTR# pin is configured to drive the active-low enable pin of an external RS485 buffer. In this configuration the DTR# pin will be forced low whenever the transmitter is not empty (LSR[6]=0), otherwise DTR# pin is high. logic [11] DTR# pin is configured to drive the activehigh enable pin of an external RS485 buffer. In this configuration, the DTR# pin will be forced high whenever the transmitter is not empty (LSR[6]=0), otherwise DTR# pin is low. If the user sets ACR[4], then the DTR# line is controlled by the status of the transmitter empty bit of LCR. When ACR[4] is set, ACR[3] is used to select active high or active low enable signals. In half-duplex systems using RS485 protocol, this facility enables the DTR# line to directly control the enable signal of external 3-state line driver buffers. When the transmitter is empty the DTR# would go inactive once the SOUT line returns to it's idle marking state.
OX16C954 rev B
ACR[5]: 950 mode trigger levels enable logic 0 Interrupts and flow control trigger levels are as described in FCR register and are compatible with 16C650/16C750 modes. logic 1 950 specific enhanced interrupt and flow control trigger levels defined by RTL, TTL, FCL and FCH are enabled. ACR[6]: ICR read enable logic 0 The Line Status Register is readable. logic 1 The Indexed Control Registers are readable. Setting this bit will map the ICR set to the LSR location for reads. During normal operation this bit should be cleared. ACR[7]: Additional status enable logic 0 Access to the ASR, TFL and RFL registers is disabled. logic 1 Access to the ASR, TFL and RFL registers is enabled. When ACR[7] is set, the MCR and LCR registers are no longer readable but remain writable, and the TFL and RFL registers replace them in the memory map for read operations. The IER register is replaced by the ASR register for all operations. The software driver may leave this bit set during normal operation, since MCR, LCR and IER do not generally need to be read.
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receiver FIFO exceeds the upper trigger level defined by FCR[7:6] as described in section 8.1. An XON is then sent when the FIFO is read down the lower fill level. The flow control is enabled and the appropriate mode is selected using EFR[3:0]. In 950 mode, the flow control thresholds defined by FCR[7:6] are ignored. In this mode, threshold levels are programmed using FCL and FCH. When in-band flow control is enabled (defined by EFR[3:0]) and the receiver FIFO level (`RFL') reaches the value programmed in the FCH register, an XOFF is transmitted to stop the flow of serial data. The flow is resumed when the receiver FIFO fill level falls below the value programmed in FCL, at which point an XON character is sent. The FCL value of 0x00 is illegal. For example if FCL and FCH contain 64 and 100 respectively, XOFF is transmitted when the receiver FIFO contains 100 characters, and XON is transmitted when sufficient characters are read from the receiver FIFO such that there are 63 characters remaining. CTS/RTS and DSR/DTR out-of-band flow control use the same trigger levels as in-band flow control. When out-ofband flow control is enabled, RTS# (or DTR#) line is deasserted when the receiver FIFO level reaches the upper limit defined in the FCH and is re-asserted when the receiver FIFO is drained below the lower limit defined in FCL. When 950 trigger levels are enabled (ACR[5]=1), the CTS# flow control functions as in 650 mode and is configured by EFR[7]. However, when EFR[6] is set, RTS# is automatically de-asserted whem RFL traches FCH and re-asserted when RFL drops below FCL. DSR# flow control is configured with ACR[2]. DTR# flow control is configured with ACR[4:3].
15.4 Transmitter Trigger Level `TTL'
The TTL register is located at offset 0x04 of the ICR Whenever 950 trigger levels are enabled (ACR[5]=1), bits 4 and 5 of FCR are ignored and an alternative arbitrary transmitter interrupt trigger level can be defined in the TTL register. This 7-bit value provides a fully programmable transmitter interrupt trigger facility. In 950 mode, a priority level 3 interrupt occurs indicating that the transmitter buffer requires more characters when the interrupt is not masked (IER[1]=1) and the transmitter FIFO level falls below the value stored in the TTL register. The value 0 (0x00) has a special meaning. In 950 mode when the user writes 0x00 to the TTL register, a level 3 interrupt only occurs when the FIFO and the transmitter shift register are both empty and the SOUT line is in the idle marking state. This feature is particularly useful to report back the empty state of the transmitter after its FIFO has been flushed away.
15.5 Receiver Interrupt. Trigger Level `RTL'
The RTL register is located at offset 0x05 of the ICR Whenever 950 trigger levels are enabled (ACR[5]=1), bits 6 and 7 of FCR are ignored and an alternative arbitrary receiver interrupt trigger level can be defined in the RTL register. This 7-bit value provides a fully programmable receiver interrupt trigger facility as opposed to the limited trigger levels available in 16C650 and 16C750 devices. It enables the system designer to optimise the interrupt performance hence minimising the interrupt overhead. In 950 mode, a priority level 2 interrupt occurs indicating that the receiver data is available when the interrupt is not masked (IER[0]=1) and the receiver FIFO level reaches the value stored in this register.
15.6 Flow Control Levels `FCL' & `FCH'
The FCL and FCH registers are located at offsets 0x06 and 0x07 of the ICR respectively Enhanced software flow control using XON/XOFF and hardware flow control using RTS#/CTS# and DTR#/DSR# are available when 950 mode trigger levels are enabled (ACR[5]=1). Improved flow control threshold levels are offered using Flow Control Lower trigger level (`FCL') and Flow Control Higher trigger level (`FCH') registers to provide a greater degree of flexibility when optimising the flow control performance. Generally, these facilities are only available in Enhanced mode. In 650 mode, in-band flow control is enabled using the EFR register. An XOFF character may be transmitted when the Data Sheet Revision 1.0
15.7 Device Identification Registers
The identification registers are located at offsets 0x08 to 0x0B of the ICR The UARTs offer four bytes of device identification. The device ID registers may be read using offset values 0x08 to 0x0B of the Indexed Control Register. Registers ID1, ID2 and ID3 identify the device as an OX16C954 and return 0x16, 0xC9 and 0x54 respectively. The REV register resides at offset 0x0B of ICR and identifies the revision of 950 core. This register returns 0x04 for the UART core in this device.
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15.8 Clock Select Register `CKS'
The CKS register is located at offset 0x03 of the ICR This register is cleared to 0x00 after a hardware reset to maintain compatibility with 16C550, but is unaffected by software reset. This allows the user to select a clock source and then reset the channel to work-around any timing glitches. CKS[1:0]: Receiver Clock Source Selector logic [00] The output of baud rate generator is selected for the receiver clock. logic [01] The DSR# pin is selected for the receiver clock. logic [10] The output of baud rate generator is selected for the receiver clock. logic [11] The transmitter clock is selected for the receiver. This allows RI# to be used for both transmitter and receiver. CKS[2]: Reserved CKS[3]: Receiver 1x clock mode selector logic 0 The receiver is in Nx clock mode as defined in the TCR register. After a hardware reset the receiver operates in 16x clock mode, i.e. 16C550 compatibility. logic 1 The receiver is in isochronous 1x clock mode. CKS[5:4]: Transmitter 1x clock or baud rate generator output (BDOUT) on DTR# pin logic [00] The function of the DTR# pin is defined by the setting of ACR[4:3]. logic [01] The transmitter 1x clock (bit rate clock) is asserted on the DTR# pin and the setting of ACR[4:3] is ignored. logic [10] The output of baud rate generator (Nx clock) is asserted on the DTR# pin and the setting of ACR[4:3] is ignored. logic [11] Reserved. CKS[6]: Transmitter clock source selector logic 0 The transmitter clock source is the output of the baud rate generator (550 compatibility). logic 1 The transmitter uses an external clock applied to the RI# pin. CKS[7]: Transmitter 1x clock mode selector logic 0 The transmitter is in Nx clock mode as defined in the TCR register. After a hardware reset the transmitter operates in 16x clock mode, i.e. 16C550 compatibility. logic 1 The transmitter is in isochronous 1x clock mode. Data Sheet Revision 1.0
15.9 Nine-bit Mode Register `NMR'
The NMR register is located at offset 0x0D of the ICR The UART offers 9-bit data framing for industrial multi-drop applications. The 9-bit mode is enabled by setting bit 0 of the Nine-bit Mode Register (NMR). In 9-bit mode the data length setting in LCR[1:0] is ignored. Furthermore as parity is permanently disabled, the setting of LCR[5:3] is also ignored. The receiver stores the 9th bit of the received data in LSR[2] (where parity error is stored in normal mode). Note that the UART provides a 128-deep FIFO for LSR[3:0]. The transmitter FIFO is 9 bits wide and 128 deep. The user should write the 9th (MSB) data bit in SPR[0] first and then write the other 8 bits to THR. As parity mode is disabled, LSR[7] is set whenever there is an overrun, framing error or received break condition. It is unaffected by the contents of LSR[2] (Now the received 9th data bit). In 9-bit mode, in-band flow control is disabled regardless of the setting of EFR[3:0] and the XON1/XON2/XOFF1 and XOFF2 registers are used for special character detection. While IER[2] is set, upon receiving a character with status error, a level 1 interrupt is asserted when the character and the associated status are transferred to the FIFO. The UART can assert an optional interrupt if a received character has its 9th bit set. As multi-drop systems often use the 9th bit as an address bit, the receiver is able to generate an interrupt upon receiving an address character. This feature is enabled by setting NMR[2]. This will result in a level 1 interrupt being asserted when the address character is transferred to the receiver FIFO. In this case, as long as there are no errors pending, i.e. LSR[1], LSR[3], and LSR[4] are clear, '0' can be read back from LSR[7] and LSR[1], thus differentiating between an `address' interrupt and receiver error or overrun interrupt in 9-bit mode. Note however that should an overrun or error interrupt actually occur, an address character may also reside in the FIFO. In this case, the software driver should examine the contents of the receiver FIFO as well as process the error. The above facility produces an interrupt for recognizing any `address' characters. Alternatively, the user can configure the UART to compare the receiver data stream with up to four programmable 9-bit characters and assert a level 5 interrupt after detecting a match. The interrupt occurs when the character is transferred to the FIFO (See below).
Interrupts in 9-Bit Mode:
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NMR[0]: 9-bit mode enable logic 0 9-bit mode is disabled. logic 1 9-bit mode is enabled. NMR[1]: Enable interrupt when 9th bit is set logic 0 Receiver interrupt for detection of an `address' character (i.e. 9th bit set) is disabled. logic 1 Receiver interrupt for detection of an `address' character (i.e. 9th bit set) is enabled and a level 1 interrupt is asserted. While the UART is in both 9-bit mode and Enhanced mode, setting IER[5] will enable detection of up to four `address' characters. The least significant eight bits of these four programmable characters are stored in special characters 1 to 4 (XON1, XON2, XOFF1 and XOFF2 in 650 mode) registers and the 9th bit of these characters are programmed in NMR[5] to NMR[2] respectively. NMR[2]: Bit 9 of Special Character 1 NMR[3]: Bit 9 of Special Character 2 NMR[4]: Bit 9 of Special Character 3 NMR[5]: Bit 9 of Special Character 4 NMR[7:6]: Reserved Bits 6 and 7 of NMR are always cleared and reserved for future use.
OX16C954 rev B
MDM[2]: Disable Trailing edge RI logic 0 Trailing edge RI is enabled. It can generate a level 4 interrupt when enabled by IER[3]. Trailing edge RI can wake up the UART when it is asleep under auto-sleep operation. logic 1 Trailing edge RI is disabled. It can not generate an interrupt or wake up the UART. MDM[3]: Disable delta DCD logic 0 Delta DCD is enabled. It can generate a level 4 interrupt when enabled by IER[3]. Delta DCD can wake up the UART when it is asleep under auto-sleep operation. logic 1 Delta DCD is disabled. It can not generate an interrupt or wake up the UART. MDM[7:4]: Reserved These bits must be set to `0000'
Special Character Detection
15.11 Readable FCR `RFC'
The RFC register is located at offset 0x0F of the ICR This read-only register returns the current state of the FCR register (Note that FCR is write-only). This register is included for diagnostic purposes.
15.10 Modem Disable Mask `MDM'
The MDM register is located at offset 0x0E of the ICR This register is cleared after a hardware reset to maintain compatibility with 16C550. It allows the user to mask interrupts, sleep operation due to individual modem lines or the serial input line. MDM[0]: Disable delta CTS logic 0 Delta CTS is enabled. It can generate a level 4 interrupt when enabled by IER[3]. Delta CTS can wake up the UART when it is asleep under auto-sleep operation. logic 1 Delta CTS is disabled. It can not generate an interrupt or wake up the UART. MDM[1]: Disable delta DSR logic 0 Delta DSR is enabled. It can generate a level 4 interrupt when enabled by IER[3]. Delta DSR can wake up the UART when it is asleep under auto-sleep operation. logic 1 Delta DSR is disabled. It can not generate an interrupt or wake up the UART.
15.12 Good-data status register `GDS'
The GDS register is located at offset 0x10 of the ICR Good data status is set when the following conditions are true: * ISR reads level0 (no interrupt), level 2 or 2a (receiver data) or level 3 (THR empty) interrupt. * LSR[7] is clear i.e. no parity error, framing error or break in the fifo. * LSR[1] is clear i.e. no overrun error has occurred. GDS[0]: Good Data Status GDS[7:1]: Reserved
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15.13 DMA Status Register `DMS'
The DMS register is located at offset 0x11 of the ICR. This allows the internal TXRDY# and RXRDY# lines to be permanently deasserted, and the current internal status to be monitored. This mainly has applications for testing. DMS[0]: RxRdy Status Read Only: set when RxRdy is asserted (pin driven low). DMS[1]: TxRdy Status Read Only: set when TxRdy is asserted (pin driven low). DMS[5:2] Reserved DMS[6]: Force RxRdy Inactive logic 0 RxRdy# acts normally logic 1 RxRdy# is permanently inactive (high) regardless of FIFO thresholds DMA[7]: Force TxRdy Inactive logic 0 TxRdy# acts normally logic 1 TxRdy# is permanently inactive (high) regardless of FIFO thresholds.
15.15 Clock Alteration Register `CKA'
The CKA register is located at offset 0x13 of the ICR. This register adds additional clock control mainly for isochronous and embedded applications. The register is effectively an enhancement to the CKS register. This register is cleared to 0x00 after a hardware reset to maintain compatibility with 16C550, but is unaffected by software reset. This allows the user to select a clock mode and then reset the channel to work-around any timing glitches. CKA[0]: Invert Receiver Clock logic 0 receiver clock as normal logic 1 receiver clock inverted (isoc apps) CKA[1]: Invert Transmitter Clock logic 0 transmitter clock as normal logic 1 transmitter clock inverted (isoc apps) CKA[2]: Invert DTR output logic 0 DTR as normal logic 1 DTR inverted CKA[3]: Use CLKSEL as System Clock logic 0 XTLI used as system clock logic 1 CLKSEL used as system clock
15.14 Port Index Register `PIX'
The PIX register is located at offset 0x12 of the ICR. This read-only register gives the UART index. This returns 0, 1, 2 or 3 depending on which UART is being accessed.
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16 OPERATING CONDITIONS
Symbol VDD VIN IIN TSTG Parameter DC supply voltage DC input voltage DC input current Storage temperature Min. -0.3 -0.3 -40 Max. 7.0 VDD + 0.3 +/- 10 125 Units V V mA C
Table 20: Absolute Maximum Ratings Symbol VDD TO Parameter DC supply voltage Operating Temperature range Min 4.75 0 Max 5.25 70 Units V C
Table 21: Recommended 5v Operating Conditions (PLCC Package) Symbol VDD TO Parameter DC supply voltage Operating Temperature range Min 3.0 0 Max 5.25 70 Units V C
Table 21b: Recommended Operating Conditions (TQFP Package Only) Note: For the TQFP package, a Voltage between 3.0 to 5.25 V is possible. The I/O switching thresholds are defined for 3.0 to 3.45 V operation with VDETECT held high, and for 4.75 to 5.25V with VDETECT held low. The thresholds are not calibrated outside these ranges, but VDETECT held high gives CMOS type I/Os that scale better with Voltage, so should be used if a voltage between these ranges is used, but the thresholds are not guaranteed.
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17 DC ELECTRICAL CHARACTERISTICS
17.1 5V Operation
Symbol VDD VIH VIL CIL COL IIH IIL VOH VOH VOL VOL IOZ IST ICC Parameter Supply voltage Input high voltage Input low voltage Capacitance of input buffers Capacitance of output buffers Input high leakage current Input low leakage current Output high voltage Output high voltage Output low voltage Output low voltage 3-state output leakage current Static current Operating supply current in normal mode Operating supply current in sleep mode Condition Commercial TTL Interface Note1 TTL Schmitt trigger TTL Interface Note 1 TTL Schmitt trigger Vin = VDD Vin = VSS IOH = 1 A IOH = 4 mA Note2 IOL = 1 A IOL = 4 mA Note2 Vin = VDD or VSS fCK = 1.8432 MHz fCK = 7.372 MHz fCK = 50.00 MHz fCK = 1.8432 MHz fCK = 7.372 MHz fCK = 50.00 MHz Min. 4.75 2.0 2.4 Max. 5.25 0.8 0.6 5.0 10.0 10 10 Units V V V pF pF A A V V V V A A mA mA
-10 -10 VDD - 0.05 2.4
-10 90 3 10 58 1.3 3.6 17.6
0.05 0.4 10 150 5 15 67
Table 22: DC Electrical Characteristics (5v)
Note 1: Note 2: All input buffers are Schmitt, with the exception of FIFOSEL, CLKSEL, INTSEL, VDETECT, I/M#. IOH and IOL are 12 mA for DB[7:0] and 4 mA for all other outputs.
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17.2 3.3V Operation
These figures assume the TQFP package with VDETECT tied high for 3.3V operation Symbol VDD VIH VIL CIL COL IIH IIL VOH VOH VOL VOL IOZ IST ICC Parameter Supply voltage Input high voltage Input low voltage Capacitance of input buffers Capacitance of output buffers Input high leakage current Input low leakage current Output high voltage Output high voltage Output low voltage Output low voltage 3-state output leakage current Static current Operating supply current in normal mode Operating supply current in sleep mode Condition Commercial TTL Interface Note1 TTL Schmitt trigger TTL Interface Note 1 TTL Schmitt trigger Vin = VDD Vin = VSS IOH = 1 A IOH = 4 mA Note2 IOL = 1 A IOL = 4 mA Note2 Vin = VDD or VSS fCK = 1.8432 MHz fCK = 7.372 MHz fCK = 50.00 MHz fCK = 1.8432 MHz fCK = 7.372 MHz fCK = 50.00 MHz Min. 3.00 0.7 VDD 1.6 Max. 3.45 0.2 VDD 1.2 5.0 10.0 10 10 Units V V V pF pF A A V V V V A A mA mA
-10 -10 VDD - 0.05 2.4
-10 40 1.1 2.4 12.9 1.1 1.8 10.9
0.05 0.4 10 150 3.1 5.2 31.0
Table 23: DC Electrical Characteristics (3v)
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18 AC ELECTRICAL CHARACTERISTICS
18.1 5V Operation
Symbol tsa tha tsc thc tr1 tr2 tacc thd tfd tw1 tw2 tsd thd Parameter Address set-up time to IOR# or IOW# falling Address hold time after IOR# or IOW# rising Chip-select set-up time to IOR# or IOW# falling Chip-select hold time after IOR# or IOW# rising Pulse duration of IOR# Delay time between IOR# rising and IOR# or IOW# falling Data valid after IOR# falling (access time) Data valid (hold) after IOR# rising Data bus floating after IOR# rising Pulse duration of IOW# Delay time between IOW# rising and IOR# or IOW# falling Data set-up time to IOW# rising Data hold time after IOW# rising Table 24: Data bus timing for Intel mode Min 0 0 0 0 29 43 0 10 29 43 0 4 ns ns ns ns ns Max Units ns ns ns ns ns ns
23
Symbol tsa tha tsrwr thrwr tdr1 tdr2 tacc tdhr tfd tsrww thrww tdw1 tdw2 tsd thdw
Parameter Address set-up time to DS# falling Address hold time after DS# rising R/W# set-up time to DS# falling (read cycle) R/W# hold time after DS# rising (read cycle) Pulse duration of DS# (read cycle) Delay to start of next read/write cycle (read cycle) Read data valid after DS# falling (access time) Read data hold data after DS# rising Data bus float after DS# rising R/W# set-up time to DS# falling (write cycle) R/W# hold time after DS# rising (write cycle) Pulse duration of DS# (write cycle) Delay to start of next read/write cycle (write cycle) Write data set-up time to DS# rising Write data valid after DS# rising Table 25: Data bus timing for Motorola mode:
Min 5 0 5 0 29 43 0
Max
23 10 5 0 29 43 0 4
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Data Sheet Revision 1.0
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OX16C954 rev B
18.2 3.3V Operation
N.B. Maximum frequency of operation is downgraded under 3V operation to 50 MHz Symbol tsa tha tsc thc tr1 tr2 tacc thd tfd tw1 tw2 tsd thd Parameter Address set-up time to IOR# or IOW# falling Address hold time after IOR# or IOW# rising Chip-select set-up time to IOR# or IOW# falling Chip-select hold time after IOR# or IOW# rising Pulse duration of IOR# Delay time between IOR# rising and IOR# or IOW# falling Data valid after IOR# falling (access time) Data valid (hold) after IOR# rising Data bus floating after IOR# rising Pulse duration of IOW# Delay time between IOW# rising and IOR# or IOW# falling Data set-up time to IOW# rising Data hold time after IOW# rising Table 26: Data bus timing for Intel mode Min 0 0 0 0 41 51 0 14 41 51 0 4 ns ns ns ns ns Max Units ns ns ns ns ns ns
32
Symbol tsa tha tsrwr thrwr tdr1 tdr2 tacc tdhr tfd tsrww thrww tdw1 tdw2 tsd thdw
Parameter Address set-up time to DS# falling Address hold time after DS# rising R/W# set-up time to DS# falling (read cycle) R/W# hold time after DS# rising (read cycle) Pulse duration of DS# (read cycle) Delay to start of next read/write cycle (read cycle) Read data valid after DS# falling (access time) Read data hold data after DS# rising Data bus float after DS# rising R/W# set-up time to DS# falling (write cycle) R/W# hold time after DS# rising (write cycle) Pulse duration of DS# (write cycle) Delay to start of next read/write cycle (write cycle) Write data set-up time to DS# rising Write data valid after DS# rising Table 27: Data bus timing for Motorola mode:
Min 5 0 5 0 41 51 0
Max
32 14 5 0 41 51 0 4
Units Ns Ns Ns Ns ns ns ns ns ns ns ns ns ns ns ns
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OX16C954 rev B
19 TIMING WAVEFORMS
A[2:0] tsa CS0#, CS1# CS2#, CS3# tsc
Address Valid tha
thc tr1
IOR#
tr2 tacc DB [7:0] Data Valid tfd thd
Figure 4: Intel Mode Read Cycle Timing
A[2:0] tsa CS0#, CS1# CS2#, CS3# tsc
Address Valid tha
thc tw1 IOW# tw2 tsd thd DB[7:0] Data Valid
Figure 5: Intel Mode Write Cycle Timing
Data Sheet Revision 1.0
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OXFORD SEMICONDUCTOR LTD.
OX16C954 rev B
TIMING WAVEFORMS
A[2:0] tsa R/W#
Address Valid tha
tsrwr tdr1 DS#
thrwr
tdr2 tacc DB[7:0] Data Valid tfd thdr
Figure 6: Motorola Mode Read Cycle Timing
A[2:0] tsa R/W#
Address Valid tha
tsrww thrw
w
tdw1 DS# tdw2 tsd DB[7:0] Data Valid thd
w
Figure 7: Motorola Mode Write Cycle Timing
Data Sheet Revision 1.0
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OX16C954 rev B
20 PACKAGE INFORMATION
OX16C954-PCC60-B
Figure 8: 68 Pin Plastic Leaded Chip Carrier
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OXFORD SEMICONDUCTOR LTD.
OX16C954 rev B
Figure 9: 68 Pin Plastic Leaded Chip Carrier
Data Sheet Revision 1.0
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OXFORD SEMICONDUCTOR LTD.
OX16C954 rev B
21 ORDERING INFORMATION
OX16C954-PCC60-B
Revision Operating Conditions -Commercial Package Type - 68 PLCC
OX16C954-TQC60-B
Revision Operating Conditions -Commercial Package Type - 80TQFP
Data Sheet Revision 1.0
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OXFORD SEMICONDUCTOR LTD.
OX16C954 rev B
NOTES
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